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Lecture 6 Logic gates : Power and Other Logic Family

Lecture 6 Logic gates : Power and Other Logic Family. Pradondet Nilagupta pom@ku.ac.th Department of Computer Engineering Kasetsart University. Acknowledgement.

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Lecture 6 Logic gates : Power and Other Logic Family

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  1. Lecture 6Logic gates :Power and Other Logic Family Pradondet Nilagupta pom@ku.ac.th Department of Computer Engineering Kasetsart University

  2. Acknowledgement • This lecture note has been summarized from lecture note on Introduction to VLSI Design, VLSI Circuit Design all over the world. I can’t remember where those slide come from. However, I’d like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide can’t be finished. 204424 Digital Design Automation

  3. b c Parasitics and Performance • Consider the following layout: • What is the impact on performance of parasitics • At point a (VDD rail)? • At point b (input)? • At Point c (output)? a 204424 Digital Design Automation

  4. Parasitics and Performance • a - power supply connections • capacitance - no effect on delay • resistance - increases delay (see p. 135) • minimize by reducing difffusion length • minimize using parallel vias a b c 204424 Digital Design Automation

  5. Parasitics and Performance • b - gate input • capacitance increases delay on previous stage (often transistor gates dominate) • resistance increases delay on previous stage a b c 204424 Digital Design Automation

  6. Parasitics and Performance • c - gate output • resistance, capacitance increase delay • Resistance & capacitance "near" to output causes additional delay a b c 204424 Digital Design Automation

  7. Driving Large Loads • Off-chip loads, long wires, etc. have high capacitance • Increasing transistor size increases driving ability (and speed), but in turn increases gate capacitance • Solution: stages of progressively larger transistors • Use nopt = ln(Cbig/Cg). • Scale by a factor of a=e 204424 Digital Design Automation

  8. Summary: Static CMOS • Advantages • High Noise Margins (VOH=VDD, VOL=Gnd) • No static power consumption (except for leakage) • Comparable rise and fall times (with proper sizing) • Robust and easy to use • Disadvantages • Large transistor counts (2N transistors for N inputs) • Larger area • More parasitic loading (2 transistor gates on each input) • Pullup issues • Lower driving capability of P transistors • Series connections especially problematic • Sizing helps, but increases loading on gate inputs 204424 Digital Design Automation

  9. Alternatives to Static CMOS • Switch Logic • nmos • Pseudo-nmos • Dynamic Logic • Low-Power Gates 204424 Digital Design Automation

  10. AND OR Switch Logic • Key idea: use transistors as switches • Concern: switches are bidirectional 204424 Digital Design Automation

  11. Switch Logic - Pass Transistors • Use n-transistor as “switches” • “Threshold problem” • Transistor switches off when Vgs < Vt • VDD input -> VDD-Vt output • Special gate needed to “restore” values IN:VDD OUT:VDD-Vtn A: VDD 204424 Digital Design Automation

  12. A’ A’ A A Switch Logic - Transmission Gates • Complementary transistors - n and p • No threshold problem • Cost: extra transistor, extra control input • Not a perfect conductor! 204424 Digital Design Automation

  13. Switch Logic Example - 2-1 MUX IN 204424 Digital Design Automation

  14. Charge Sharing • Consider transmission gates in series • Each node has parasitic capacitances • Problems occur when inputs change to redistribute charge • Solution: design network so there is always a path from VDD or Gnd to output 204424 Digital Design Automation

  15. Aside: Transmission Gates in Analog • Transmission Gates work with analog values, too! • Example: Voltage-Scaling D/A Converter 204424 Digital Design Automation

  16. OUT Pulldown Network NMOS Logic • Used before CMOS was widely available • Uses only n transistors • Normal n transistors in pull-down network • depletion-mode n transistor (Vt < 0) used for pull-up • "ratioed logic" required • Tradeoffs: • Simpler processing • Smaller gates • higher power! • Additional design considerationsfor ratioed logic Passive Pullup Device:depletion Mode n-transistor (Vt < 0) 204424 Digital Design Automation

  17. OUT Pulldown Network Pseudo-nmos Logic • Same idea, as nmos, but use p-transistor for pullup • "ratioed logic" required for proper design (more about this next) • Tradeoffs: • Fewer transistors -> smaller gates, esp. for large number of inputs • less capacitative load on gates that drive inputs • larger power consumption • less noise margin (VOL > 0) • additional design considerations due to ratioed logic Passive Pullup Device: P-Transistor 204424 Digital Design Automation

  18. Idp OUT Pulldown Network Idn Ratioed Logic for Pseudo-nmos • Approach: • Assume VOUT=VOL =0.25*VDD • Assume 1 pulldown transistor is on • Equate currents in p, n transistors • Solve for ratio between sizes of p, n transistors to get these conditions • Further calculations necessary for series connections 204424 Digital Design Automation

  19. OUT OUT’ OUTPulldownNetwork OUT’PulldownNetwork A A’ B B’ C C’ DCVS Logic • DCVS - Differential Cascode Voltage Switch • Differential inputs, outputs • Two pulldown networks • Tradeoffs • Lower capacitative loading than static CMOS • No ratioed logic needed • Low static power consumption • More transistors • More signals to route between gates • Example: Fig. 3.29 p. 148 204424 Digital Design Automation

  20. f CS Precharge Signal StorageCapacitance Pulldown Network B A C Precharge Evaluate Precharge f Dynamic Logic • Key idea: Two-step operation • precharge - charge CS to logic high • evaluate - conditionally discharge CS • Control - precharge clock f Storage Node 204424 Digital Design Automation

  21. f CS Pulldown Network B C f in4 x1 f x2 x3 Domino Logic • Key idea: dynamic gate + inverter • Cascaded gates - “monotonically increasing” 204424 Digital Design Automation

  22. Domino Logic Tradeoffs • Fewer transistors -> smaller gates • Lower power consumption than pseudo-nmos • Clocking required • Logic not complete (AND, OR, but no NOT) 204424 Digital Design Automation

  23. More Techniques for Saving Power • Reduce VDD (tradeoff: delay) • Multiple Power Supplies • High VDD for “fast” logic • Low VDD for “slow” logic • (level translation an issue) • DCSL - Fig. 3-35, p. 155 • cross-coupled outputs • partially disconnected pulldown network • Dealing with leakage currents (p. 158) • Multiple-Threshold CMOS (MTCMOS) - Fig 3-37 • Variable-Threshold CMOS (VTCMOS) - Fig 3-38 204424 Digital Design Automation

  24. Delay in Long Wires - Lumped RC Model • What is the delay in a long wire? • Lumped RC Model: • Delay time constant (ignoring driving gate) t = R * C = (Rs * L / W) * (L * W * Cplate )= r * c * L2 • Problem: Overly Pessimistic R = Rs * L / W = r*L (r = Rs / W - resistance per unit length ) C = L * W * Cplate = c*L(c = W * Cplate - capacitance per unit length) 204424 Digital Design Automation

  25. Delay in Long Wires - Distributed RC Model • Alternative: Break wire into small segments • Approx. Solution - 1st moment of impulse response • Important: delay still grows as square of length 204424 Digital Design Automation

  26. Delay in Long Wires - Consequences in design • Distributed RC model: • Delay grows as square of L! • Choose wire material that minimizes r, c • Break wire into buffered segments to optimize delay 204424 Digital Design Automation

  27. Elmore Delay • Consider R-C ladder network with unequal values • First-order time constant at node N is • First-order time constant and node I is 204424 Digital Design Automation

  28. Elmore Delay Applications • Wire sizing to minimize delay • Delay prediction of complex networks (as long as they take the form of a ladder) 204424 Digital Design Automation

  29. Elmore Delay Homework Problem • What are the Elmore time constants t1, t2, t3? 204424 Digital Design Automation

  30. Wire Sizing • Recall distributed model of wire: multiple segmentsnote strong impact of R1, lesser impact of R2, etc • Idea: Reduce overall delay by tapering segments • Make Segment 1 widest to reduce R1 (increases C1) • Make Segment 2 less wide to reduce R2 (increses C2) • etc. 204424 Digital Design Automation

  31. Wire Sizing • Ideal Result wire should taper exponentially- see Eq. 3-20, p. 163 [Fis95]: • More pragmatic approach: step-tapered wire [Fis95] J. Fishburn and C. Schevon, “Shaping a distributed-RC line to minimize Elmore delay”, IEEE Trans. on Circuits and Systems-I, December 1995, pp. 1020-1022 204424 Digital Design Automation

  32. in out Buffer Insertion • Key Idea: Break long wire up into stages (Sec. 3.7.3) • Equivalent Circuit: Fig. 3-44, p. 167 • 50% delay of each segment: Eq 3-35 • Number of stages for minimum delay: Eq 3-36 • Best size and number of stages: Eq 3-38 - 3-39 204424 Digital Design Automation

  33. Wire Sizing - New Results • Alternative approach [Alpert01]: • Combine buffer insertion and • Untapered wires of (small number of) different widths • Theoretical result: Tapering gives at best 3.5% improvement over this approach • Practical result: tapering generally not worthwhile [Alpert01] “Interconnect Synthesis without wire tapering”, IEEE Trans. CAD, Vol. 20, No. 1, January 2001, pp. 90-104 204424 Digital Design Automation

  34. Delay in RC-Trees • Many interconnection networks are trees • Extracted RC circuit modeling a gate output • Clock trees 204424 Digital Design Automation

  35. Delay in RC-Trees: Penfield-Rubenstein Bounds • Key idea: characterize time constants in terms of • Path resistances between nodes • Capacitance values at each node 204424 Digital Design Automation

  36. Delay in RC-Trees: Penfield-Rubenstein Bounds • Time constants Tp, TDo, TRo (eqn. 3-30 - 3-34) • Table 3-2 (p. 165) - bounds for time, voltage 204424 Digital Design Automation

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