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Peak Temperature Estimation in VLSI Circuits

Peak Temperature Estimation in VLSI Circuits. Speaker: Ya-Hsin Chang Advisor: Chun-Yao Wang 03/13/09. Outline. Introduction Methods Experimental Results Conclusion Future Work. Introduction.

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Peak Temperature Estimation in VLSI Circuits

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  1. Peak Temperature Estimation in VLSI Circuits Speaker: Ya-Hsin Chang Advisor: Chun-Yao Wang 03/13/09

  2. Outline • Introduction • Methods • Experimental Results • Conclusion • Future Work

  3. Introduction • With increasing number of transistor and clock frequency, peak temperature can be more than 136℃ • High temperature can degrade the reliability ,and it also has significant impact on performance, cooling and packaging cost • Peak temperature estimation can serve as guidelines for boundaries and limits of circuit

  4. Introduction • Peak temperature depends on both heat generationfrom power consumption and heatdissipation to ambient air

  5. Introduction • For convenience, we can divide a chip into blocks for thermal modeling

  6. Power Dissipation • Leakage power dissipation • Short-circuit power dissipation • Dynamic power dissipation VDD IL Vin Vout IS ID GND

  7. Power Dissipation • Since the processing and structure parameters have been fixed, we focus on dynamic power consumption model: Input Vector V1 Input Vector V2 Combinational Logic Combinational Logic Find out the peak power

  8. Outline • Introduction • Methods • Experimental Result • Conclusion • Future Work

  9. Initial Solutions • Construct initial solutions • Randomize 10,000 input pattern pairs • Pick top 3 high transition hotspots 52 48 50

  10. Ant Colony Optimization (ACO) • The communication between ants is based on the use of chemicals, called pheromones, produced by the ants Food Nest

  11. A A’ Ant Colony Optimization (ACO) • Pheromone update • After feeding each pair of input vectors, we can get the switching frequency of an area

  12. Local Search • Use GA (Genetic Algorithm) for local search • For each input pin, pick extreme large τ value by deviation

  13. 11001 → 10010 00101 → 10011 11000 → 01011 10001 → 01101 … 11000 → 01101 … Local Search Top 100 patterns 1X00X→ 0X10X Mutation Crossover Mutation

  14. Ant Colony Optimization • To avoid getting trapped in local optimum: • Good allocation for GA patterns • Add half amount of random patterns in each ACO operation • Evaporate pheromoneto avoid unlimited accumulation of pheromone trails

  15. Flow Chart Update hotspot queue Hotspots START Update pheromone & Pheromone evap. Construct initial solutions Hotspot queue=0 || Reach terminal condition Get suspicious hotspots N Y END Local search

  16. Outline • Introduction • Methods • Experimental Results • Conclusion • Future Work

  17. Power Estimation • Due to the constraints of input and output data files, we cannot find an appropriate tool which can satisfy our demands • Estimate each transition power by HSPICE .MEAS TRAN Pand3 AVG P(Xand3) from=0 to=100ns Input frequency = 100Mhz

  18. Temperature Calculation Flow Chart Read in packaged chip Thermal model is based on HotSpot4.0 Calculate R matrix Calculate B matrix B T = Power LU decomposition on B Power file LU solve on B Temperature file

  19. Simulation Mode • Phe_table += FSwitch / N_FGate • Phe_table += FPower / N_FGate

  20. Output Patterns Best pattern Boundary value If ( FSF > B_FSF || FSF==B_FSF && SF > B_SF) Then pushback to the queue Calculate T of 100 patts. at the end of the program SW mode If ( totalP > B_totalP) Then calculate T If(T > B_T) Then pushback to the queue Power mode

  21. C432 Temperature Map

  22. Results of zero delay model

  23. Results of delay model

  24. The comparison btw different block size

  25. Outline • Introduction • Methods • Experimental Results • Conclusion • Future Work

  26. Conclusion • Our program produces the higher peak temperature from random • Avg. 21.04%, max 33.09% in zero delay • Avg. 42.47%, max 45.34% in delay model • Output the hotspot location and temperature profile for design convenience • Considered different design stage

  27. Conclusion • As expected, the hotspot located in the framed area • The framed size is critical – 50x50um2 • The runtime of our program can be long due to mass blocks • <=20 blocks is recommended

  28. Thermal Modeling Accuracy Analysis • Lower bound of the unit size • Chip thickness = 150μ • 5.0% : w = 30μ • 2.5% : w = 15μ • 1.5% : w = 10μ

  29. Future Work • Continue programming work • Try to improve performance by adjusting controlling variable in the experiment • Ex: Different input frequency, block size…

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