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Hardware design methodology Fault avoidance during design Design documentation

332:437 Lecture 3 Hardware Design Methodology and Advanced Logic Design http://www.caip.rutgers.edu/~bushnell/dsdwebsite/dsdwebpage.html. Hardware design methodology Fault avoidance during design Design documentation History of logic design Logic design definitions Karnaugh Maps Summary.

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Hardware design methodology Fault avoidance during design Design documentation

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  1. 332:437 Lecture 3Hardware Design Methodologyand Advanced Logic Designhttp://www.caip.rutgers.edu/~bushnell/dsdwebsite/dsdwebpage.html • Hardware design methodology • Fault avoidance during design • Design documentation • History of logic design • Logic design definitions • Karnaugh Maps • Summary Material from An Engineering Approach to Digital Design, By William I. Fletcher, Prentice-Hall Inc. Bushnell: Digital Systems Design Lecture 3

  2. Hardware Design Methodology • Very important, exists at every hardware manufacturer • Iterative • Design Process • Problem definition – need a clear, concise English statement • System Requirements – created from problem definition • Reliability • Cost • Weight • Power consumption • Physical size • Performance (Speed) • Maintainability • Compatibility with existing designs Bushnell: Digital Systems Design Lecture 3

  3. System Partitioning • Break into manageable subsystems, each to be designed by teams of engineers • Subsystem must be easy to handle • Based on hardware performance requirements & propagation delay or • Based on reliability requirements (aerospace) • Flight-critical • Mission-critical • Convenience-functions Bushnell: Digital Systems Design Lecture 3

  4. Hardware Concept Development • Create several candidate designs • High-level analysis • Analyze each candidate architecture • Reliability estimate • Cost estimate • Weight estimate • Testability estimate • Power estimate • Eliminate some candidate designs • PROBLEM: Need detailed information to get reliable estimates Bushnell: Digital Systems Design Lecture 3

  5. Hardware and Software Specifications • “Detailed plan for a design that can meet certain requirements” • Hardware software design & analysis • Carry out for each candidate design that survived High-Level Analysis • Keep analyzing designs as they are filled out to make sure that they meet system requirements • Testing & Design for Testability • Search for faults of all types • Design mistakes • Implementation mistakes • Component defects Bushnell: Digital Systems Design Lecture 3

  6. System Integration and Test • Combine hardware & software in a system prototype • Example – software that never created problems on a hardware emulator may cause problems on the actual hardware • Usually due to assumptions coded in the emulator that are not fulfilled by the actual hardware Bushnell: Digital Systems Design Lecture 3

  7. Fault Avoidance During Design • Requirements Design Review • Conceptual Design Review • Specifications Design Review • Important to have a testable design • Detailed Design Review – most important • Final Design Review – last checkpoint in design process • Check that working prototype meets specifications • Parts Selection • Trade-off • Part cost vs. part failure rate • Part availability vs. failure rate • Cost of a part failure • Has critical impact on system reliability and availability Bushnell: Digital Systems Design Lecture 3

  8. Design Rules and Documentation • Packaging • Testing • Electrical Shielding • Circuit Layout • Documentation • Must be clear & correct Bushnell: Digital Systems Design Lecture 3

  9. History of Logic Design • 340 BC – Logic invented by Aristotle • 1854 – George Boole recognized that Aristotleian logic can be represented symbolically as Boolean algebra • 1938 – Claude Shannon showed that switching circuits could be analyzed using Boolean algebra Bushnell: Digital Systems Design Lecture 3

  10. Duality • Axioms and Theorems – come in pairs • Get one of the pair from the other by: • Replacing AND with OR • Replacing OR with AND • Replacing 1 with 0 • Replacing 0 with 1 • If E is a valid Boolean expression, then Ed (its dual) is also valid Bushnell: Digital Systems Design Lecture 3

  11. Canonical Forms • Literal – switching variable or its complement (e.g., x or y) • Product Term or Implicant – series of literals related by AND operator • Sum Term –Series of literals related by OR operator Bushnell: Digital Systems Design Lecture 3

  12. Minterm # 5 13 A 0 1 B 1 1 C 0 0 D 1 1 Minterm A B C D A B C D Karnaugh Maps • Terminology • Logical Adjacency – 2 product terms that differ in just 1 variable • f (A, B, C, D) = … + A B C D + A B C D + … (A + A) (B C D) B C D Bushnell: Digital Systems Design Lecture 3

  13. Karnaugh Maps • Let t be a product term in some SOP representation of f • t is an implicant if the input patterns that make t a 1 always make f a 1 • t is a prime implicant if deletion of any literal term from t creates a product term that is not an implicant of f • Key observation: • In a minimal SOP form for f (), all product terms are prime implicants • Variable-Entered Karnaugh Map – invented by Maurice Karnaugh of IBM Bushnell: Digital Systems Design Lecture 3

  14. AB CD 00 01 11 10 00 1 0 1 1 11 1 1 0 1 01 0 1 1 0 10 0 0 1 0 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 Karnaugh Map f (A, B, C, D) = S (0, 3, 2, 5, 7, 11, 12, 13, 14) f (A, B, C, D) = P (1, 4, 6, 8, 9, 10, 15) Bushnell: Digital Systems Design Lecture 3

  15. x z x 1 z y O T z x 2 y x y Sum of Products (SOP) andProduct of Sums (POS) Bushnell: Digital Systems Design Lecture 3

  16. Sum of Products (SOP) andProduct of Sums (POS) • Minimal 2-level SOP form: • No equivalent expression with fewer products • No equivalent expression with the same # of products but smaller # of variables in products Bushnell: Digital Systems Design Lecture 3

  17. AB C 0 1 00 1 01 1 11 1 1 10 1 1 Simplifying Kmaps • Determine smallest set of groups that covers all minterms • Note: Cover first the 1’s you can’t cover any other way (these are essential prime implicants) • Example: f (A, B, C) = Sm (0, 3, 4, 5, 6, 7) • Note: Covers can overlap Bushnell: Digital Systems Design Lecture 3

  18. A B 0 1 1 1 1 0 0 1 Can Also Use Minimal POS • Group 0’s • Realize each group as a sum term with variables being complements of the SOP term • Example 1: f (A, B) = A + B • f (A, B) = (A + B) Bushnell: Digital Systems Design Lecture 3

  19. AB CD 00 01 11 10 00 1 0 0 1 01 0 0 0 0 11 1 0 0 1 10 0 0 1 1 0 1 3 2 4 5 7 6 12 13 15 14 8 9 11 10 Example 2 • f (A, B, C, D) = PM (1, 3, 4, 5, 6, 7, 8, 9, 13, 15) • f = (A + D) (A + B) (B + D) (A + B + C) Bushnell: Digital Systems Design Lecture 3

  20. Logic Circuit Incompletely Specified Functions • What if not all 2N combinations happen? • Introduce don’t cares into K-maps – represent as X’s 2N input patterns • f (w, x, y, z) = Sm (0, 7, 8, 10, 12) + d (2, 6, 11) • d signifies a don’t care or X value N Bushnell: Digital Systems Design Lecture 3

  21. Differing Circuit Cost Measures • # logic gates and # gate inputs • # of inputs on a printed circuit board • # of VLSI chips needed for the circuit • Chip area required by the circuit on a VLSI chip • Power required by the circuit on a VLSI chip • We used to use 1, 2, and 3. Now we use 4 and 5 (entire circuit is on 1 chip) • 1 – traditional • 2 – 1980’s • 3 and 4 – 1990’s • # chip inputs, 4, and 5 – 21st Century Bushnell: Digital Systems Design Lecture 3

  22. Critically Important Issues • Reduce circuit power consumption • Make the circuit fast – get rid of all unnecessary gate delays, keep total wire length short • Make it possible to test the circuit – get rid of all unnecessary or redundant logic and insert extra hardware to make testing possible • To find minimal circuit realization: • Find minimal SOP realization • Find minimal POS realization • Choose smaller of 1 and 2 or use Quine-McCluskey algorithm to optimize logic Bushnell: Digital Systems Design Lecture 3

  23. Summary • Hardware design methodology • Fault avoidance during design • Design documentation • History of logic design • Logic design definitions • Karnaugh Maps Bushnell: Digital Systems Design Lecture 3

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