Design ITWG ITRS Conference, San Francisco July 16, 2003 San Francisco Europe: Ralf Brederlow

1. Design ITWG ITRS Conference, San Francisco July 16, 2003 San Francisco • Europe: Ralf Brederlow • Japan: Ichiro Yamamoto, Tamotsu Hiwatashi, Koichiro Ishibashi • Taiwan: Chung-Ping Chen • U.S.: Andrew Kahng, Resve Saleh, Dennis Sylvester

2. Design ITWG Contributions to ITRS • System Drivers Chapter • Defines IC products that drive manufacturing and design technologies • ORTCs + System Drivers = framework for technology requirements • SoC-centric organization, with three “fabrics” • Processor • Mixed-Signal • Memory • Design Chapter • Cross-cutting challenges: (1) productivity, (2) power, (3) design for manufacturing, (4) interference, (5) error-tolerance • Design cost and productivity models • Technology areas: (1) design process, (2) system-level design, (3) logical/physical/circuit design, (4) design verification, (5) design test • ORTC support • Frequency, Power, Density models

3. Big Picture • Message: Cost of Design threatens continuation of the semiconductor roadmap • Design cost model • Challenges are now Crises : software, verification, analog, cost... • Strengthen bridge from semiconductors to applications, software, architectures • Hertz and bits are not the same as efficiency and utility • System Drivers chapter, with productivity and power foci • Strengthen bridges among ITRS technologies • “Shared red bricks” can be solved (or, worked-around) more cost-effectively variability, low-k, leakage, … • “Manufacturing Integration” cross-cutting challenge • “Living ITRS” framework to promote consistency validation

4. SYSTEM DRIVERS CHAPTER

5. System Drivers Chapter Outline 2001 • Scope • High-volume custom (MPU, memory), AMS, SOC • Market Drivers • MPU • Mixed-Signal • SoC • Multi-Technology • High-Performance • Low-Cost, Low-Power • Trends (Power and Design Productivity, based on LP-PDA model)

6. System Drivers Chapter Changes High priority • Rewriting and reorganization  SOC-centric structure • SOC LP PDA model • Table 10 (Performance and die size, Device and memory composition) • Battery technology • Mixed-signal content • SOC LP Device Table 11/36 reconciliation • Embedded memory section Low priority, deferred until 2004-2005 • SOC impact of cost drivers • SIP Multi-Technology integration alternatives; low metal/mask count • Embedded DSP, MCU • Off-chip signaling bandwidth

7. SoC Taxonomy Component Fabrics: Processor, Memory, Mixed-Signal

8. System Drivers Chapter Outline 2001 2003 • Market Drivers • SoC scope and taxonomy • Multi-Technology, High-Performance, Cost-Driven • Component Fabrics • MPU • Mixed-Signal • Memory • SoC trends • LP-PDA and Power • Cost and SiP integration • Scope • High-volume custom (MPU, memory), AMS, SOC • Market Drivers • MPU • Mixed-Signal • SoC • Multi-Technology • High-Performance • Low-Cost, Low-Power • Trends (Power and Design Productivity, based on LP-PDA model)

9. SoC Taxonomy Component Fabrics: Processor, Memory, Mixed-Signal

10. 2003 ITRS Low-Power PDA Model • (R. Saleh, K. Uchiyama, I. Yamamoto) • Goals • Validate existing models and modify results based on any new data • Modify ITRS System Drivers text accordingly

11. Trends of Digital Consumer Products 2000 1990 Mobile information terminal STB Digital TV PDA Next generation Video game 32/64b Video game MPEG camera Video CD LAN router DVD player Digital Still camera Car navigation CIS AutoPC Mobile phone (GSM,CDMA,..) Portable MultiMedia Products

12. Req’d Performance for Multi-Media Processing GOPS 0.01 0.1 1 10 100 Video MPEG1 Extraction Compression MPEG2 Extraction MP/ML MP/HL MPEG4 JPEG Audio Voice Sentence Translation Dolby-AC3 Voice Auto Translation MPEG Word Recognition Graphics 3D Graphics 10Mpps 100Mpps 2D Graphics Communication Recognition SW Defined Radio VoIP Modem Face Recognition Modem Voice Print Recognition Moving Picture Recognition FAX GOPS: Giga Operations Per Second

13. ITRS SoC Low-Power PDA Model Study • Reference Design: personal digital assistant (PDA) • Composed of CPU, DSP, peripheral I/O, and memory

14. Example SoC for PDA 0.18um / 400MHz / 470mW (typical) MM Application MP3 JPEG SimpleMoving Picture CPG PWR Processor Area PWM RTC CPU FICP SSP 6.5MTrs. I2C I-cache 32KB GPIO D-cache 32KB Sound Max 400MHz USB USB OST Specification DMA controller MMC MMC I2S Available Time 6-10Hr LCD Cnt. MEM Cnt. KEY UART AC97 Data Transfer Area LCD Flash 32MB SDRAM 64MB Peripheral Area 100MHz 4 – 48MHz

15. PDA Model Characteristics

16. 2003 ITRS Low-Power PDA Model • (R. Saleh, K. Uchiyama, I. Yamamoto) • Goals • Validate existing models and modify results based on any new data • Modify ITRS System Drivers text accordingly • Outcomes • Keep power-related projections • Remove productivity-related projections • Table 1: Reduction of GOPS values, inclusion of battery technology advances  decided to stay with original version • Gate leakage, mixed-signal content, eSRAM-eDRAM transition point  also left unchanged • Many refinements, but conclusions do not change

17. LSTP Power Dissipation

18. LOP Power Dissipation

19. Power-Constrained Chip Composition Memory Logic

20.  Technology Needs (e.g., Design) • Multi-everything optimization • Mix of HP, LOP, LSTP devices in same core • Design tools must simultaneously optimize use of Vdd, Vt, Tox knobs as well as device sizing • Body bias control • Dynamic voltage, frequency scaling • Clock gating • Sleep modes • Operating system and application control • Other technology area needs: PIDS, A&P, Test…

21. Analog / Mixed-Signal Update • Adapted to analog & RF technologies for wireless communications working group within PIDS • System Drivers Chapter text aligned with the new PIDS subchapter • Drivers and Figures of Merit • ADC: stays as predicted • LNA: stronger performance improvement than expected in 2001 • VCO: FoM is adjusted to technology (some changes in text) • Numbers remain relatively similar • Benefits from certain technology measures as expected, but VCO improvement versus technology remains weak part of RF circuits • PA: stays as predicted • Still CMOS-centric; some enhancements with other technologies must occur when looking at SiP

22. Embedded Memory • SRAM, Flash, DRAM technology parameters • Cell size, additional masks, area efficiency • Access time, power active/standby, refresh, lifetime, SEU • Figure of Merit for memory: • 1/ (cell size * area efficiency * mask-count factor * effective power (static or dynamic) * access time (R or RW)) • Define Drivers and their needs • Granularity and hierarchy • Volatile/non-volatile storage • Code (size?) vs. data (size?  voice, image, …) • Bandwidth vs. storage trade-off • Error correction codes, testability, yield

23. DESIGN CHAPTER

24. Design Chapter Outline 2001 • Scope of DT • Traditional landscape… • Complexity Challenges • Methodology Precepts • Design Technology Challenges • Design Process • System-Level • Logic/Circuit/Physical • Verification • Test • Metrics/Table • Appendix: DT Cost, Value

25. Design Chapter Changes • Canonical design flow context, design system architecture and design process • Design cost model refinement • Standalone analog CAD, circuits, SOI content • Soft-error (including logic) • Rewriting and reorganization • Interactions with other ITWGs • Ground rules (poly half-pitch, contacted M1 pitch, …) impact on layout density • Benefits of, and lower bounds for, technology improvements (dielectric permittivity, CD variability, …) • Off-chip signaling roadmap • High-performance (MPU) system power requirements

26. Design Chapter Outline 2001 2003 • Scope of DT • DT Cost and Value Analysis • Complexity Challenges • Design Technology Challenges with respect to System Drivers • SOC and MPU • Overview • Design process ++ • System-level • Logic/Circuit/Physical • Verification • Test • Mixed-Signal (Europe) • [Memory (Europe)] • Metrics/Table • Scope of DT • Traditional landscape… • Complexity Challenges • Methodology Precepts • Design Technology Challenges • Design Process • System-Level • Logic/Circuit/Physical • Verification • Test • Metrics/Table • Appendix: DT Cost, Value

27. Design Process • (J. Darringer, D. Cottrell, T. Hiwatashi, G. Martin, G. Smith) • Merge Design Process and Methodology Precepts • Organize Challenges around 5 Key Trends • Tight Coupling • Design for Manufacture • Increasing Level of Abstraction • Increasing Level of Automation • Early Verification • New Figure 16 to show evolution and trends • Based on STRJ-WG1 Canonical Flow • Different methodologies or applications would have variant flows • Show implied evolution of design system architecture • New Table 13 to summarize challenges and strategies

28. Canonical Design Flow (STRJ-WG1) • Provides context for detailed technology discussions • Also serves as grounding for design cost analysis • Required Design Technology innovations • RTL synthesis • = synthesis technology that creates RT-level models from architecture models • HW/SW co-synthesis • = synthesis technology that creates architecture models from behavior models • I.e., outputs architecture models for HW and source codes for SW

29. Full/Semi-Automated Handcraft Files, Documents System Requirement Analysis Design FlowRTL Synthesis System Requirement Specification System Function Design System Architecture Design HW Specification SW Specification Micro Architecture Design(Block Partition) Modeling Verification Software Development Behavior Models & Constraints RTL Synthesis RTL Models & Constraints Logical & Physical Design Mask Data Hardware Development

30. Full/Semi-Automated Handcraft Files, Documents System Requirement Analysis Design FlowHW/SW Co-Synthesis System Requirement Specification System Function Design Modeling Verification System Behavior Model ,Design Constraint HW/SW Co-Synthesis Behavior Models & Constraints SW Source Code RTL Synthesis Software Development RTL Models & Constraints Logic design & Physical Design Mask Data Hardware Development

31. Revised ITRS Design Cost Model • (J.-A. Carballo, G. Smith) • Description of model • Rewritten to further clarify model, data, and conclusions • Introduced footnotes to explain geographical issues • Will remain an Appendix in 2003 Design Chapter • Model itself • Introduced cost model tree to capture key components • Included software design in tree • Accomodates canonical design flows • Data • Performed substantial sanity checks  successful overall • Future versions will emphasize software, large-block reuse • Calibration across regions (salary, productivity data) due to market differences should be resolved in future versions

32. Chip/circuit/physical design Cost Model Tree Chip integration Labor Verification, test Product cost SW development EDA integration & support Development R&D EDA licenses Test chips Infrastructure Manufacturing Depreciation/amortization Marketing, sales Key: General, administrative design/development costs other costs Maintenance, service Financial

33. Major Cost Components Labor Unit Cost X Design Complexity ____________________________ Design Labor Cost = Designer Productivity EDA Unit Cost X Design Complexity __________________________ EDA Infrastructure Cost = Designer Productivity

34. Productivity Evolution

35. CAD for Analog / Mixed-Signal / RF To close the productivity gap, must focus on: • Description languages (analog and digital, electrical and non-electrical) • System performance evaluation and design-space exploration • Circuit synthesis and sizing • Schematic validation • Design for manufacturing • Analog/RF layout synthesis • Parasitic extraction, modeling, and simulation • Analog IP and reuse • Top-down and bottom-up methodologies

36. Expected Breakthroughs in AMS CAD

37. SUMMARY

38. Summary • System Drivers Chapter • New material • Embedded memory • Improvements to existing material • “SOC-centric” chapter reorganization • SOC Low-Power PDA driver model • MPU, Mixed-Signal discussions • Design Chapter • New material • Analog section • Canonical design flow context • Improvements to existing material • Design cost model • Design process and design system architecture

39. THANK YOU !