Parallel Routing for FPGAs based on the operator formulation

1. Parallel Routing for FPGAs based on the operator formulation Yehdhih Ould Mohamed Moctar & Philip Brisk Department of Computer Science & Engineering University of California Riverside Design Automation Conference (DAC 2014) San Francisco, CA, USA, June 1-5, 2014

2. Motivation • Runtime of circuit design is dominated by P&R • Maze Expansion consumes over 65% of Runtime • Large number of non-conflicting operations executed at each iteration

3. Contribution • Application of Speculative Parallelism to FPGA routing • Use of non-blocking priority queues for the Maze Expansion • Implementation of the parallel router in VPR

4. FPGA Routing • Find a physical path for every signal in the circuit • Disjoint-path problem; NP-complete S T1 T2 • Pathfinder: Negotiation-based algorithm

5. Routing Resource Graph (RRG) source wire3 wire4 2-LUT out out wire3 wire4 in2 in1 wire2 wire1 in2 in1 wire1 wire2 sink • RRG represents the routing resources of the FPGA 5

6. Serial Pathfinder We Parallelize the Maze Expansion

7. Maze Expansion Operation • PQ contains nodes that have not been fully explored

8. Galois • Software framework for parallelizing irregular algorithms • Employ speculation based approach to parallelism • Operator formulation of algorithms Parallel program = Operator + Schedule + Parallel data structure

9. Operator formulation of algorithms • Operator • Computation at active element • Activity: application of operator to active element • Amorphous data-parallelism • Multiple active nodes can be processed in parallel subject to neighborhood and ordering constraints : active node : neighborhood Parallel program = Operator + Schedule + Parallel data structure 9

10. Maze Expansion in Galois • Threads speculatively explore the node of RRG • Each Thread has a local Priority Queue

11. Benchmarks • We selected 10 of the largest IWLS benchmarks. • We target 65nm CMOS (BPTM)

12. Maze Router Speedup • Achieved up-to 5.5x speedup (Using 8 threads) • Steady Scalability up to 8 threads

13. Maze Router – Configuration Options (Normalized Speedup) • STM PQ + Iteration Coalescing achieved 5.46x speedup

14. Maze Router - Critical Path Delay (CPD) • # of Threads has no impact on Critical Path Delay (CPD) • Parallel implementation achieved better CPD than VPR

15. Conclusion & Future Work • Speculative parallelism can be good choice for parallel • CAD algorithms • Achieved Near-linear speedup (up to 5.5x) over • Serial FPGA Router. • Future work includes applying this speculative • model to parallelize Placement.