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ISUAL Mass Memory

ISUAL Mass Memory. Robert Abiad. Outline. Description Requirements Interfaces Block Diagram Usage Scheme Parts Development Status. Description. 2.6 GBit organized as 64 M x 40 bits 32 bit data word

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ISUAL Mass Memory

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  1. ISUAL Mass Memory Robert Abiad

  2. Outline • Description • Requirements • Interfaces • Block Diagram • Usage Scheme • Parts • Development Status NCKU UCB Tohoku Mass Memory R. Abiad

  3. Description • 2.6 GBit organized as 64 M x 40 bits • 32 bit data word • 7 bit Error Correction Code per word corrects all single bit errors and detects all double bit and some multiple bit errors. • Samsung K4S560832A-TL1H 256 Mbit base device organized as 32M x 8bit. NCKU UCB Tohoku Mass Memory R. Abiad

  4. Requirements • Store data from Imager at 8M pixel/s data rate • Store data from Array Photometer at 20k samples/s x 32 channels/sample = 640k channels/s • Store data from Spectrophotometer at 10k samples/s x 6 channels/sample = 60k channels/s • Read telemetry data at 1.6 Mb/s • Allow read/write from DPU • Allow read/write from DCM NCKU UCB Tohoku Mass Memory R. Abiad

  5. Mass Memory Interfaces 12 Imager DATA IDC/ Mass Memory CLK DATA 2 SP CLK 2 ENA 2 DATA-1 AP Telemetry DATA-2 CLK CLK DATA ENA DATA DPU ENA ENA CLK 32 DCM DATA 26 ADDR BUSY NCKU UCB Tohoku Mass Memory R. Abiad

  6. Priorities • Imager • Memory Refresh • Telemetry • Array Photometer • Fast Spectrophotometer • Slow Spectrophotometer • DPU • DCM NCKU UCB Tohoku Mass Memory R. Abiad

  7. Mass Memory Block Diagram Imager Data Interface 32MB SDRAM 32MB SDRAM AP SP DPU 32MB SDRAM 32MB SDRAM DCM Level Shift TLM 32MB SDRAM 32MB SDRAM Address Interface 32MB SDRAM 32MB SDRAM Level Shift 32MB SDRAM 32MB SDRAM NCKU UCB Tohoku Mass Memory R. Abiad

  8. Usage Scheme A A • Circular buffers • Fill on trigger • N Pretrigger • M Posttrigger • Buffer switch Buffer Allocation N Trigger M B Buffer Allocation NCKU UCB Tohoku Mass Memory R. Abiad

  9. SAMSUNG SDRAM • Latch up immune up to 82 MeV/(mg/cm²) • Radiation hardened to 17-40 kRad total dose • SEU susceptibility mitigated by EDAC • Parts received • Parts will be lot tested to verify radiation tolerance NCKU UCB Tohoku Mass Memory R. Abiad

  10. Development Status • Parts selection • All major parts ordered • Usage schemes designed • Address interfaces designed • Memory controller designed • Issues • FPGA speed limitations • FPGA device selection NCKU UCB Tohoku Mass Memory R. Abiad

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