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ΗΥ220 Εργαστήριο Ψηφιακών Κυκλωμάτων

ΗΥ220 Εργαστήριο Ψηφιακών Κυκλωμάτων. Χειμερινό Εξάμηνο 200 7 -200 8 Παράδειγμα : PCI Bus. PCI Bus Pin List. Initiator Target. PCI Commands. Command Type C/BE[3:0]# Interrupt Acknowledge 0000 Special Cycle 0001

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ΗΥ220 Εργαστήριο Ψηφιακών Κυκλωμάτων

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  1. ΗΥ220Εργαστήριο Ψηφιακών Κυκλωμάτων Χειμερινό Εξάμηνο 2007-2008 Παράδειγμα: PCI Bus ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  2. PCI Bus Pin List ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  3. Initiator Target ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  4. PCI Commands Command Type C/BE[3:0]# • Interrupt Acknowledge 0000 • Special Cycle 0001 • I/O Read 0010 • I/O Write 0011 • Memory Read 0110 • Memory Write 0111 • Configuration Read 1010 • Configuration Write 1011 • Memory Read Multiple 1100 • Dual Address Cycle 1101 • Memory Read Line 1110 • Memory Write and Invalidate 1100 ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  5. Basic Read Operation ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  6. Basic Write Operation ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  7. Basic Arbitration ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  8. Master Initiated Termination • Completion : The master has concluded its intended transaction. • Timeout : Termination when the master’s GNT#_ is deasserted and its internal Latency Timer has expired. ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  9. Master Abort Termination ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  10. Master Initiated Termination ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  11. Target Initiated Termination • Retry : Termination requested before any data is tranferred. • Disconnect : Termination requested with or after data was transferred on the initial phase because the target is unable to respond within the target subsequent latency requirement, and is temporarily unable continue bursting. • Target Abort : Adnormal termination requested because the target detected a fatal error or the target will never be able to complete the request. ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  12. Target Initiated Termination Signaling Rules 1/2 • A data phase completes on the rising edge on which IRDY# is asserted and either STOP# or TRDY# is asserted. • Independent of the state of STOP#,a data transfer takes place on every rising edge of clock where both IRDY# and TRDY# are asserted. • Once the target asserts STOP#, it must keep STOP# asserted until FRAME# is deasserted, whereupon it must deassert STOP#. ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  13. Target Initiated Termination Signaling Rules 2/2 • Once a target has asserted TRDY# or STOP#, it cannot change DEVSEL#, TRDY# or STOP# until the current data phase completes. • Whenever STOP# is asseted, the master must deassert FRAME# as soon as IRDY# can be asserted. • If not already deasserted, TRDY#, STOP#, and DEVSEL# must be deasserted the clock following the completion of the last data phase and must be tri-stated the next clock. ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  14. Target Initiated Termination 1/2 ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  15. Target Initiated Termination 2/2 ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  16. Disconnect-1 Without Data Termination ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  17. Disconnect-2 Without Data Termination ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  18. Retry ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  19. PCI Configuration Header ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  20. Status Register Bit Assignmet ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  21. Command Register Bit Assignmet ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

  22. Base Address Register Format ΗΥ220 - Β.Παπαευσταθίου & Γ. Καλοκαιρινός

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