1 / 10

TK2633

TK2633. 8085 Microprocessor Architecture – Demultiplexing the AD7-AD0. DR MASRI AYOB. Bus Demultiplexer AD 7 -AD 0. It is necessary to have the knowledge and skills to demultiplex data bus and address bus as it is important in hardware design applications.

koto
Download Presentation

TK2633

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. TK2633 8085 Microprocessor Architecture – Demultiplexing the AD7-AD0 DR MASRI AYOB

  2. Bus Demultiplexer AD7-AD0 • It is necessary to have the knowledge and skills to demultiplex data bus and address bus as it is important in hardware design applications. • Like previous example (referring to timing diagram): MOV C,A => with machine code (4FH)

  3. Bus Demultiplexer AD7-AD0 Figure 1

  4. Bus Demultiplexer AD7-AD0 • From fig 1, to run instruction MOV C, A the high order address bus maintained as bus address for three clock periods. • However the low order address bus (05H) was eliminated after first time state. • The address need to be latched as to identify memory address. • After T1, the bus AD7-AD0 now becomes 4FH.

  5. Schematic diagram to latch low order address bus. 05H Figure 2

  6. Bus Demultiplexer AD7-AD0 • In Fig 2, the AD7-AD0 bus is connected to the input of latch buffer 74LS373. • The ALE signal is connected to enable pin (G) at latch, and the output control signal is grounded (OC). • When the ALE signal is active high, the latch will act according to the input instruction (the output changes according to input data). • At T1 the latch output value is 05H, and when ALE is low, the byte data 05H is hold until the new next ALE signal activated. • This causes the output latch is low order address memory A7-A0 (05H).

  7. Control Signals • It is necessary to generate two RD control signals, one for memory and one for peripheral. • Similar to WR control signal; one for writing to memory and one for writing to output peripheral.

  8. Control Signals Figure 3: Example of schematic diagram to generate control signals.

  9. Control Signals and Demultiplexing Figure 4:the combination of control signals as well as demultiplexing the bus system.

  10. Thank youQ&A

More Related