Overview for 1149.1 Initialization Process

1. Overview for 1149.1 Initialization Process April 27, 2010

2. Configurable I/O • Since the original development of the 1149.1 Boundary Scan standard, the complexity and variation of I/O cells as well as the ICs themselves has greatly increased in the digital IC industry • Process technology advancements have reduced the safe operating voltage ranges of transistors • I/Os are now configurable for the electrical characteristics such as power levels, drive strength, VIL/VIH, impedance, etc. • Unused I/O may be configured to be power downed and to not actually be capable of receiving logic values placed on the pin for lower power modes • In both mission and test modes, I/Os frequently require configuration before they can be used

3. Boundary Scan Operation Failures • I/O cannot correctly drive or receive a logic 1 or 0 until the correct configuration for the given instance is loaded and known • Mismatched configurations of I/Os on a board could cause a driven logic 1 to be received as a logic 0 • In mission mode, a powered-off I/O analog cell cannot SAMPLE the pin value to the BSR • Until an Initialization Procedure is completed to program or configure the I/O, none of 1149.X instructions which control or observe the pins can be reliably depended on to correctly operate

4. IC Initialization for “Safe” operation for Board-level Interconnect Test • It may be desirable or necessary to place an IC into a “safe” mode during Board-level tests • If board interconnect tests are performed before attachment of heat sinks, it may be necessary to power down large portions of IC core for thermal management • To reduce power consumption, PLLs may need to be disabled during board level interconnect testing • Without setting the I/O voltage level program correctly, incorrect applied input signal voltage may permanently damage an I/O cell • Chips with Secure information may require the deletion of data before Boundary operations

5. Initialization Procedure • All of these issues can be resolved by Initialization procedure • The proposed Initialization procedure support needs to allow for the following: • Optional parameterized configuration by setting data in a TDR (INIT_DATA) • Optional specification a minimum number of TCKs (or other time value) for configuration completion to take effect (either for a state machine execution or a “settling time”) • Option to receive status bits • Option to “poll” for earlier completion • Control of when the mission mode is disrupted

6. Overview • 2 instructions: • INIT_SETUP (optional INIT_DATA TDR) • INIT_RUN (optional INIT_STATUS TDR) • Run after POR, before EXTEST • NOT dependent on RTI TAP state • BSDL to document the data fields of INIT_DATA) with optional mnemonics for field values, Completion time, and optional expected results (format, content TBD) • Side file to specify per chip instance initialization data and expected results

7. Board Test Control of Chip State During Test • Board tests consist of series of 1149.1 based tests • Each test starts and ends at Test-Logic-Reset during potential glitching of TRST* during transition between tests • Need for a some optional persistence of a “Test Safe” state after a Test-Logic-Reset and before a normal mission-mode reset • The INIT_DATA values can be re-usable TLR  INIT_SETUP  [INIT_RUN]  EXTEST  TLR  [INIT_RUN]  EXTEST • The Test Safe state should tend to persist

8. Modes of Usages • Initialization can be used under different types of usages across different chips on the same Boundary scan chain at the board level • No Initialization required (Chips stay in BYPASS) • Direct Parameterization: with INIT_SETUP only, followed by EXTEST (No Completion Time requirement) • Simple State Machine Execution: INIT_RUN only with Completion Time required followed by EXTEST (No parameterization required) • Parameterized State Machine Execution: Initialization with INIT_SETUP for parameterization, then INIT_RUN for Completion Time before EXTEST

9. BSDL Updates for Initialization • BSDL will have new Attributes and Keywords for Initialization • Update INSTRUCTION_OPCODE to add INIT_SETUP and INIT_RUN in • Update REGISTER_STATUS to add INIT_DATA and INIT_STATUS • Create REGISTER_MNEMONICS Attribute to describe optional mnemonics for data fields • Create REGISTER_FIELDS to define the subfields of the INIT_DATA or INIT_STATUS register sub-fields

10. Side file • The side file is specific to each instantiation of chip supporting Initialization on the board • Side file would provide the parameterization required per instance • Side file would facilitate tool inter-operability • Based in based PDL constructs from P1687 • File supplies the data values for the INIT_DATA values

11. Initialization Flow • UpdateIR INIT_SETUP on chips which support it; other chips are in BYPASS • ShiftDR INIT_DATA TDR to set parameters • Parameters can control the electrical settings of the I/Os per board specifics • IOs may support a wide range of electrical settings which may not be able to signal correctly without initialization • Parameters can control system internals as well. e.g. power-downs, PLL Kill, etc. for safe operation

12. Initialization Flow • PRELOAD instruction should be run before INIT_RUN to initialize the data path values • At UpdateIR, INIT_RUN starts execution to place chip in state ready for EXTEST* • Intrusive • Internal state machines may be executing for a Completion time to do the state changes • ShiftDR will shift either optional INIT_STATUS or BYPASS TDR • The board must wait until last chip has completed • Completion is define by either a Completion time or by a Done Status provided by INIT_STATUS TDR

13. Flow TestLogicReset Initial TAP State UpdateIR INIT_SETUP / BYP Some chips in BYPASS mode; chip state undisturbed ShiftDR INIT_SETUP / BYP Load INIT params per chip as needed into INIT_DATA UpdateIR / ShiftDR PRELOAD Initialize the data values into the BSR

14. Flow (Con’t) Invasive; FSM starting running if any chips need it UpdateIR INIT_RUN / BYP Initialization operating (not TLR) Any State of TAP ShiftDR INIT_RUN / BYP Some chips in BYPASS mode; INIT_STATUS or BYPASS output INIT_RUN Done After max Completion Time or INIT_STATUS Done indicated EXTEST operation with correct data and electrical values UpdateIR EXTEST*