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RADIX-2 DECIMATION IN TIME (DIT) FFT IMPLEMENTATION BASED ON A MATRIX-MULTIPLE CONSTANT MULTIPLICATION APPROACH. 1,2 Sidinei Ghissoni, 3 Eduardo Costa, 4 Cristiano Lazzari, 4 José Carlos Monteiro, 4 Levent Aksoy, 1 Ricardo Reis

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  1. RADIX-2 DECIMATION IN TIME (DIT) FFT IMPLEMENTATION BASED ONA MATRIX-MULTIPLE CONSTANT MULTIPLICATION APPROACH 1,2Sidinei Ghissoni, 3Eduardo Costa, 4Cristiano Lazzari, 4José Carlos Monteiro, 4Levent Aksoy, 1Ricardo Reis 1PGMICRO-UFRGS, Porto Alegre, RS-Brazil {sghissoni, reis}@inf.ufrgs.br 2 UNIPAMPA-Alegrete, RS, Brazil Sidinei.Ghissoni@unipampa.edu.br 3 UCPEL, Pelotas–RS-Brazil ecosta@ucpel.tche.br 4 INESC-IST, Lisboa, Portugal {jcm,lazzari,aksoy}@inesc-id.pt, ICECS2010- Athens Greece

  2. Outline Motivation Goals Related Works Matrix-MultipleConstant Multiplication FFT Architecture Results Conclusions Future Works ICECS2010- Athens Greece

  3. Motivation The optimization of FFT architectures; The FFT architectures are widely used in signals processing application; The use of multipliers in FFTs requires large area and power consumption; Thus we intend to optimize the multipliers by using M-MCM and gate level approaches ICECS2010- Athens Greece

  4. Goals The main goal is the implementation of fully-parallel radix-2 Decimation in Time (DIT) Fast Fourier Transform – FFT, using the Matrix- Multiple Constant Multiplication (M-MCM) at gate level, whose comparison of area and power can be realized at the same conditions of behavioral synthesis. ICECS2010- Athens Greece

  5. Fast Fourier Transform The Fast Fourier Transform (FFT) is an important algorithm used in many DSP applications, such as audio and video process, wireless communication, and it is also found in modules of WLAN (Wireless Local Area Network) chips. ICECS2010- Athens Greece

  6. Fast Fourier Transform (FFT) Where is the Twiddle factor [1] Curley, 1965. The algorithm of Curley, 1965 [1], is a simpler form to calculate the Discrete Fourier Transform (DFT) efficiently: ICECS2010- Athens Greece

  7. FFT-Radix-2 Decimation in Time Decimation in Time The FFT radix-2 for DIT is the following: ICECS2010- Athens Greece

  8. Related Works L. Jia, Y, 1998. Can effectively minimize the number of complex multiplications in pipelined FFTs; In K. Stevens, 1998. An optimization of FFT architecture based on multirate signal processing and asynchronous circuit technology is proposed. ICECS2010- Athens Greece

  9. Related Works J.-E. Oh and M.-S. Lim, 2005, proposed the optimization of the twiddle factors using trigonometric identity for few points of FFT architecture. In W. Han, 2008, the solutions are based on parallel architectures for high throughput and power efficient FFT cores . M. D. Macleod, 2005 minimize the adder-cost (the number of additions and subtractions), while achieving a specified level of accuracy, but it takes much more processing time, with the increasing of data wordlength; ICECS2010- Athens Greece

  10. Related Works O. Gustafsson, 2006, 2007, 2008 and Y. Voronenko and M. P¨uschel, 2007 present the use of sharing in multipliers for decrease area; F. Qureshi, Gustafsson, 2009, present reconfigurable complex constant multiplication for FFTs based on trigonometric identidad in each estage; Levent, 2008, Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. ICECS2010- Athens Greece

  11. y1 y2 . . . yn x1 x2 . . . xn a11 a12 … a1n a21 a22 … a2n . . . am1 am2 … amn = Matrix-Multiple Constant Multiplications (M-MCM) a11x1 + a12x2 + ... + a1nxn a21x1 + a22x2 + ... + a2nxn . . . am1x1 + am2x2 + ... + amnxn X = ICECS2010- Athens Greece

  12. x1 x2 y1 y2 17 24 9 3 = Matrix-Multiple Constant Multiplications Example : ICECS2010- Athens Greece

  13. A 0 0 3b 1b 4b B 0 5b 1b 0 0 0 #FA=5 #HA=1 A 1b 5b 1b 1b B 0 5b 1b 0 #FA=6 #HA=1 ApplicationofGateLevel(7) • A + B<<1 • S=1 nA=8 nm=7 • nB=6 nM=8 • FA FA HA Wire • A + B<<3 • S=3 nA=8 nm=8 • nB=6 nM=9 • FA FA HA Wire [7] L. Aksoy at al, 2007. ICECS2010- Athens Greece

  14. Design Flow DIT-FFT Behavioral Architecture Vhdl Constant (Twiddle factor ) of the DIT-FFT MMCM at gate level Algorithms Generation of vhdl ModelSim Encounter RTL Encounter RTL Comparison ICECS2010- Athens Greece

  15. Implementation of 16-point Radix-2 DIT FFT ICECS2010- Athens Greece

  16. Results FFT architectures were implemented in order to demonstrate the efficiency of the proposed method. The radix-2 DIT FFT implementation with logic synthesis was performed with the CADENCE Encounter RTL Compiler tool for the UMC 130nm technology: ICECS2010- Athens Greece

  17. Conclusion The use of the MMCM can reduce area and power of fully-parallel FFT significantly, when compared with the synthesis of commercial EDA with behavioral implementation; An FFT architecture can be implemented using only adders/subtracters. Thus, it can allow the use of other type of more efficient adders/subtracters. ICECS2010- Athens Greece

  18. Future Works Apply MMCM at gate level metric with more efficient adders such as CSA , and 4:2, 8:2 and 16:2 adder compressors for semi-parallel and serial FFT architectures on behalf of the optimization of area, power and delay; ICECS2010- Athens Greece

  19. Thank you! Questions? ICECS2010- Athens Greece

  20. RADIX-2 DECIMATION IN TIME (DIT) FFT IMPLEMENTATION BASED ONA MATRIX-MULTIPLE CONSTANT MULTIPLICATION APPROACH 1,2Sidinei Ghissoni, 3Eduardo Costa, 4Cristiano Lazzari, 4José Carlos Monteiro, 4Levent Aksoy, 1Ricardo Reis 1PGMICRO-UFRGS, Porto Alegre, RS-Brazil {sghissoni, reis}@inf.ufrgs.br 2 UNIPAMPA-Alegrete, RS, Brazil Sidinei.Ghissoni@unipampa.edu.br 3 UCPEL, Pelotas–RS-Brazil ecosta@ucpel.tche.br 4 INESC-IST, Lisboa, Portugal {jcm,lazzari,aksoy}@inesc-id.pt, ICECS2010- Athens Greece

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