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Lecture 11 Instruction Sets and Addressing Modes

Lecture 11 Instruction Sets and Addressing Modes. Readings. Stalling, Sections 10.1, 10.2, 10.4, 11.1, 11.3 Tutorial Handout. Language Hierarchy (1). High level language FORTRAN, COBOL, Algol 60 & 68. Pascal, C, Modula. Smalltalk, C++, Java, Python. SQL, Prolog, Haskell, Miranda, Hope.

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Lecture 11 Instruction Sets and Addressing Modes

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  1. Lecture 11Instruction SetsandAddressing Modes

  2. Readings • Stalling, Sections 10.1, 10.2, 10.4, 11.1, 11.3 • Tutorial Handout

  3. Language Hierarchy (1) • High level language • FORTRAN, COBOL, Algol 60 & 68. • Pascal, C, Modula. • Smalltalk, C++, Java, Python. • SQL, Prolog, Haskell, Miranda, Hope. • Design of processor is of no concern.

  4. Language Hierarchy (2) • Assembly language • Mnemonics (abbreviations) are used for the instructions of the processor. • Names for memory locations. • Labels. • Symbols. • Design of processor must be known.

  5. Language Hierarchy (3) • Machine language • Instructions are patterns of ones and zeros. • This is what the processor actually uses.

  6. Assembly vs Machine Language • Direct correspondence between machine language and assembly language. • Assembly language is easier for humans to read and understand than machine language. • A program, called an assembler, translates assembly language into machine language. • Why assembly language?

  7. Simple Example • Write the instructions to add 50 and 72 and save the answer. • HLL: • X  50 + 72;

  8. OP Code Destination Source Typical Instruction Format Label: OP D, S ; comments

  9. Simple Example • Write the instructions to add 50 and 72 and save the answer. • HLL: X  50 + 72;

  10. Assembly Language MVI A, 50H MVI B, 72H ADD B MOV C, A HLT

  11. Machine Language HEX BINARY COMMENTS 3E 0011 1100 MVI A 32 0011 0010 50H 36 0011 0110 MVI B 48 0100 1000 72H 80 1000 0000 ADD B 4F 0100 1111 MOV C, A 76 0111 0110 HLT

  12. Instruction Set • The set of operations provided by a processor. • Determined by the design and implementation of the processor. • Restrictions imposed by: • size, speed and complexity of the chip. • target application.

  13. Instruction Format • Instructions consists of one or more fields: • Operation code field (opcode) • Operand field(s) – presence and number depends upon the instruction.

  14. 8085 Programmer’s Model

  15. 8085 Programmer’s Model (continued) • Seven 8-bit registers: • A, B, C, D, E, H, L. • Register A is the accumulator. • Three 16-bit registers (register pairs): • B & C, D & E, H & L. • PC: Not directly addressable. • SP: Stack pointer.

  16. 8085 Programmer’s Model (continued) • 8-bit status register (PSW): • Contains flag bits denoting the result of the last operation performed. • Some instructions operate on the accumulator and PSW as a register pair.

  17. Instruction Types • Data transfer or movement. • Arithmetic. • Logical. • Branching (transfer of control). • Processor Control.

  18. Data Transfer Instructions(Load/Store) • Moves data between registers and memory locations (or between memory and stack). • Input and output to external devices. • Some processors require data to be moved via a register when moving between 2 memory locations. • Move is really a copy operation – source location is not altered.

  19. Data Transfer Example 1 • Load the accumulator with the data byte 82H and save the data in register B. MVI A, 82H MOV B, A

  20. Data Transfer Example 2 • Read eight on/off switches connected to the input port with the address 00H and turn on the corresponding devices connected to the output port with the address 01H. IN 00H OUT 01H

  21. Arithmetic • Add • Subtract • Increment • Decrement • Multiply • Divide

  22. Logical • Logical AND • Logical OR • Exclusive OR • Complement (NOT) • Compare • Shift left/right • Rotate left/right • Set/reset bits

  23. Branching(Transfer of Control) • Jump, call, and return. (Unconditional/Conditional). • Call and return used for subroutines. Typically place the address of the next instruction on a stack and return to the location on the stack. • Restart. • Interrupt.

  24. Conditional Branching • Positive/negative • Zero/not zero • Carry/not carry • Parity odd/parity even

  25. Processor Control • Halt • Enable/disable interrupts • Read/set interrupt mask • No operation.

  26. Addressing Multiple Locations • Some data types require more than one byte. • Some memory systems store several bytes at one location (address). • Order is important and must be known. • 8085 stores low order byte first. • JMP 2046 is stored C3,46,20

  27. Number of Operands • An ADD requires three addresses – two operands and a result. • The addresses may be explicit or implicit. • Implicit addresses  fewer operands shorter instructions. • However, cost may be more instructions to set up conditions.

  28. Reducing the Number of Operands • Use the accumulator for one source and the result. • Thus only one source operand is required for many instructions. • Known as 1-address instruction type. 2-, 3- and even 4-address types are known.

  29. Reducing the Number of Operands • Could be reduced to no operands by having all implied. • The penalty is data transfer to get the operands into the correct locations before the ADD instruction. • Some processors use a stack architecture. • Trade-off between program size, speed of execution, and ease of programming.

  30. Addressing Modes • The way in which the operands are specified. • Options are: • data is specified in the instruction, • data is in a register or memory location, • address of data is in a register or memory location. • Calculation of effective address.

  31. Addressing Modes at a Restaurant • Pass the butter (Immediate). • Specifies the exact item. • Pass the bowl (Register). • Let us eat. • The location is implicit - the plate in front of you. Similar to the instruction CMA where the contents of the accumulator are complemented. No operand is required.

  32. Addressing Modes at a Restaurant (continued) • I will have combination 17 on the menu. • The location of the item on the menu is specified and not the actual item. • Similar to the instruction to transfer the data byte from the location 2040.

  33. Addressing Modes at a Restaurant (continued) • I will have what Susie ordered. • The order is specified indirectly. The server has to look at what Susie ordered to know what you want. • Similar to an instruction that specifies a memory location through the contents of a register pair or another memory location.

  34. Addressing Modes Immediate Register Register indirect Address (memory location) Indirect Displacement Relative addressing Base-register addressing Indexed addressing Stack

  35. Addressing Modes (continued)

  36. Immediate Addressing Mode • The operand (data value) is provided as part of the instruction. • Used to: • manipulate constants. • set initial values of variables. • Example: MVI B, 20H

  37. Register Addressing • The operand is contained in a register which is specified in the instruction. • Example: MOV C, B

  38. Direct Addressing • The address of the operand is specified in the instruction. • Example: ADD 1020 • An assembler allows the use of named memory locations. • Example: ADD BETA • Names (labels) can also be used for branching. • Example: JMP LOOP

  39. Indirect Addressing • The address in the operand field is that of a memory location which contains the address of the operand. • ADD (1025)

  40. Indirect Addressing

  41. Register Indirect Addressing • The specified register contains the address of the operand.

  42. Displacement Addressing (In General) • Combines the capabilities of direct addressing and register indirect addressing. • Requires two address fields, at least one must be explicit. • One field is used directly - A. • Other field (may be implicit) refers to a register whose contents are added to A to give the address.

  43. Displacement Addressing (In General) • EA = A + ( R ) • Three common uses • relative addressing • base-register addressing • indexed addressing

  44. Displacement Addressing (In General)

  45. Displacement Addressing (Relative Addressing) • The effective address is the sum of the address field (offset) and the program counter. • Exploits the concept of locality. • ADD @10

  46. Displacement Addressing (Base-Register Addressing) • The referenced register contains an address. • The address field contains a displacement. • Similar to relative addressing. • ADD (R3)@10.

  47. Displacement Addressing (Indexed Addressing) • The address field references a memory location. • The register contains a displacement. • Opposite of base-register addressing. • ADD 1020@R2.

  48. Stack Addressing • Usually a special processor design. • Instruction does not have any operands. • Operands are placed on a stack. • Result is left on the stack.

  49. Next Lecture Assembly Language Programming 1

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