CHARGE COUPLING TRUE CDS PIXEL PROCESSING

1. CHARGE COUPLINGTRUE CDS PIXEL PROCESSING 2.8 e- CMOS photon transfer True CDS CMOS pixel noise data

2. FULL WELL / NONLINEARITY 3T PHOTO DIODE PIXEL FULL WELL DEPENDENT ON PHOTO DIODE CAPACITANCE NONLINEAR RESPONSE CAUSED BY PHOTO DIODE CAPACITANCE DEPENDENCE ON SIGNAL NONLINEARITY MAY BE ADVANTAGEOUS FOR EXTENDED DYNAMIC RANGE 5T / 6T CHARGE COUPLE PIXEL FULL WELL DEPENDENT ON SENSE NODE CAPACITANCE LINEAR RESPONSE BECAUSE SENSE NODE IS DECOUPLED FROM PHOTO REGION SOURCE FOLLOWER GATE CAPACITANCE CAN BE MADE TO BE DOMINATE SENSE NODE CAPACITANCE FOR GOOD LINEARITY

3. 3T FULL WELL RAW VIDEO

4. 3T LINEARITY

5. PHOTO GATE FULL WELL

6. PHOTO GATE LINEARITY

7. CHARGE TRANSFER EFFICIENCY CHARGE COUPLED SURFACE CHANNEL PIXEL SURFACE STATE DENSITY FOR CMOS IS CONSIDERABLY GREATER THAN CCD EXHIBITS POOR CTE PERFORMANCE BECAUSE OF INTERFACE TRAPS CTE SENSITIVE TO HIGH ENERGY RADIATION SOURCES CHARGE COUPLED BURIED CHANNEL PIXEL EXHIBITS EXCELLENT CTE PERFORMANCE RAD HARD CTE PERFORMANCE

8. NOISE VARIANCE

9. CHARGE COUPLED PG PIXEL

10. SURFACE vs BURIED CHANNEL CTE BURIED CHANNEL SURFACE CHANNEL

11. SURFACE CHANNEL PHOTOGATE 250 krad PRE RAD

12. CMOS DARK CURRENT DARK CURRENT IS THE MOST LIMITING PERFORMANCE PARAMETER FOR CMOS IMAGERS DARK CURRENT IS THE MOST DIFFICULT PARAMETER TO UNDERSTAND AND LOWER SURFACE STATE DENSITY IS SIGNIFICANTLY GREATER THAN CCD. HENCE, HIGHER DARK CURRENT MPP CCD < 10 pA/cm^2 3T CMOS pixel > 0.5 nA/cm^2 CUSTOM CHARGE COUPLED PINNED PHOTO DIODE CMOS PIXELS < 30 pA/cm^2 DARK CURRENT PROBLEMS LIMITED H2 ANNEALING DURING CMOS FABRICATION HIGH FIELD ASSISTED DARK CURRENT GENERATION SHALLOW TRENCH ISOLATION (STI) DARK CURRENT LUMINESCENCE GATE LEAKAGE OXIDE TUNNELING SILICON WAFER ISSUES (QUALITY, PROPER GETTERING, etc.)

13. 3T PHOTODIODE DARK CURRENT BACKSIDE FRONTSIDE

14. INVERTED BURIED CHANNEL PHOTO GATE OPERATION

15. CMOS RAD HARDNESS IONIZATION DAMAGE 3T READ MOSFETS (RESET, ROW SELECT AND SOURCE FOLLOWER) EXHIBIT VERY LITTLE LEAKAGE AND FLAT BAND SHIFT IN REACTION TO 1 Mrd Co-60 RADIATION SOURCE FOLLOWER FLICKER NOISE INCREASE THERMAL DARK CURRENT INCREASE BULK DAMAGE DARK SPIKES (HOT PIXELS) QE LOSS WITHIN NON DEPLETED MATERIAL

16. FLAT BAND SHIFT(ROW SELECT MOSFET)

17. PHOTON TRANSFER CHARACTERISTICS 3T DEEP N WELL

18. DARK CURRENT AND DARK SPIKES DARK SPIKES 10 krd DARK CURRENT 1 Mrd

19. CMOS ARRAY PROBLEMS FOR SCIENTIFIC PERFORMANCE ON-CHIP CMOS FEATURES OFTEN DEGRADE FUNDAMENTAL PIXEL PERFORMANCE e.g. ANALOG TO DIGITAL CONVERTER (ADC) LIMITS PERFORMANCE TO 12 BIT DYNAMIC RANGE INFLEXIBILITY TO CHANGE CRITICAL PIXEL TIMING AND READOUT MODES e.g., 3T, 5T, 6T PIXEL CLOCKING ROLLING SHUTTER, PROGRESSIVE SCAN AND SNAP READOUT INABILITY TO CHANGE CDS TIMING, SYSTEM BANDWIDTH, GAIN AND OFFSET INABILITY TO CLOCK PIXELS WITH DRIVE VOLTAGES GREATER THAN VDD INABILITY TO CONTROL,GROUND AND FILTER REGULATED VOLTAGES EXTERNALLY SCIENTIFIC CMOS ARRAYS ARE BEING DESIGNED WITH THESE LIMITATIONS IN MIND (e.g. ALLOW OFF CHIP ADC)

20. HYBRID ARRAYS: CMOS TO CMOS Frame rate vs array size 512 x 512 sparse bumped “monolithic mosaic.”

21. HYBRID ARRAYS: CMOS TO CMOS ↑ CMOS pixel array CMOS ROIC array voltage compatible. ↑ CMOS pixel array is fabricated independently from ROIC array (allowing pixel optimization and isolation). ↑ Sparse bumping can take place within the array. ↑ Tolerant to high-energy radiation sources. ↑ Very high resolution – ultra high speed operation. ↑ Read noise independent of array size or frame rate. ↑ Low power / compact sensor designs. ↓ High cost for custom pixel CMOS processing.