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DCS planning for ITS/SDD

DCS planning for ITS/SDD. Vojtech Petracek Jiri Kral CTU Prague DCS workshop 13.3.06 - CERN. Current status of the SDD/DCS. LV – modules in production, good progress in SW, running module/SW reliability tests

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DCS planning for ITS/SDD

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  1. DCS planning for ITS/SDD Vojtech Petracek Jiri Kral CTU Prague DCS workshop 13.3.06 - CERN

  2. Current status of the SDD/DCS • LV – modules in production, good progress in SW, running module/SW reliability tests • HV – necessary hardware just arrived, we can start development of controls (OPC, ISEG) • FE – well advanced preparation on both HW & SW fronts • COOLING – preparation of the patch panel • PVSS – still more training needed, first application in PVSS coming soon

  3. HV • crate and ISEG module arrived 2 days ago to CERN, so that we can start with DCS development. It should be quite straightforward, but it will take time till 1.5.

  4. LV • all LVPS modules will be delivered at the end of April • After that they will be tested and burned-in at CERN and used for ladder operation at Torino • DCS software for crate ready, in few weeks will be linked to PVSS • Neutron test passed, module OK after 10^9 n/ cm^2 • Design of patch panel for cooling interlock signal distribution is ongoing (signal specification from cooling group needed!) • Well be ready for rudimental DCS during the SDD-SSD integration (August->) • Fabrication of crate controllers from 1.5.06.

  5. FE • 25 DCS boards being finalized at KIP/HD • Production of LVDS expander boards (1.4) • Implementation of cabling as-if the DCS board is in shoebox (1.6.) • DCS board and Ladder running @ Torino running • Well be ready also for rudimental DCS during the SDD-SSD integration (August->) • We need the CARLOS board to test the real setup, up to now we are using DILBERT chip on development board.

  6. External driver board prototype successfully tested with DCS, Carlos and LV left and right boards first production in 2 weeks

  7. Cooling • As soon as we receive specification of the interlock signal, we finalize the patch panel for distribution of the interlock to relevant LVPS module sections.

  8. PVSS • we’ll start the top level in few weeks to be ready with first version of PVSS controls for all sections by the time of ITS integration • Another student will be working on it – all together we will be working on this problem with ~2.5persons.

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