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CM-5 Massively Parallel Supercomputer

CM-5 Massively Parallel Supercomputer. Thinking Machines Corporation. ALAN MOSER. 1993. CM-5 General Information. Brain child of W. Daniel Hillis Lewis W. Tucker Founded Thinking Machines Corporation in the 1980’s CM-5 was last in a line of successors to the

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CM-5 Massively Parallel Supercomputer

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  1. CM-5 Massively Parallel Supercomputer Thinking Machines Corporation ALAN MOSER 1993

  2. CM-5 General Information Brain child of W. Daniel Hillis Lewis W. Tucker Founded Thinking Machines Corporation in the 1980’s CM-5 was last in a line of successors to the original CM-1 Connection Machine

  3. CM-5 Connection MachineHardware Overview 32-16384 processing nodes each of which contain a 32 MHz SPARC RISC processor 32 MB of distributed memory although the size may vary according to customer specifications 128 Mflops (per processing node) yielding a total performance of 1Teraflops. Tera=2^40 or roughly 10^12

  4. Processing Node vs. Processor Processing Node not a single processor but a set of 5 chips Single 32 MHz SPARC RISC processor with 4 separate vector units capable of performing 64 bit floating point and integer arithmetic

  5. Diagram of Processing Node

  6. CM-5 Operating System CM-5 runs the CMOST OS enhanced version of the UNIX OS Each processing node contains a microkernal of the OS

  7. CM-5 MIMD or SIMD Machine? Referred to as synchronized MIMD machine somewhere between MIMD and SIMD best aspects of both types of machines

  8. CM-5 Batch Processing or Timesharing? CM-5 allows both Batch processing and Timesharing Timesharing is provided by dividing processing nodes into a partition controlled by partition manager Protection is enforced by hardware so that one partition cannot interfere with another

  9. Interconnection Network(s) What? CM-5 has not one but three overlapping interconnection networks Data Network Control Network Diagnostic Network

  10. 3 Overlapping Interconnection Networks

  11. CM-5 Data Network Supports simultaneous sending of messages between processing nodes Solves several problems: balancing message loads in network “fetch-deadlock problem” timesharing a parallel computer

  12. CM-5 Data Network Binary fat tree

  13. CM-5 Data Network (cont.) Messages are passed between processing nodes using the least common ancestor Increasing bandwidth at each level up Avoids “bottlenecks” at the root node

  14. CM-5 Control Network Designed a simple tree Provides synchronization so as to allow CM-5 to operate like SIMD computer In general control network provides for: fast broadcasting of data barrier synchronization parallel prefix/postfix scan operations

  15. CM-5 Diagnostic Network Organized as incomplete binary tree Able to map-out or ignore parts of the tree that are faulty Able to select and access groups of system chips in parallel including: single chip single type of chip chips within a user partition chips associated within portion of the system such as board, cabinet, etc.

  16. CM-5 Diagnostic Network Diagram

  17. References “The Network Architecture of the Connection Machine CM-5”, Thinking Machines Corporation February 7, 1996 Hillis, Daniel and Tucker, Lewis “The CM-5 Connection Machine: A Scalable Supercomputer” Communications of the ACM, November 1993 Volume 36, Number 11

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