1 / 11

Teaching Functional Verification – Course Organization

Teaching Functional Verification – Course Organization. Design Automation Conference Sunday, June 9, 2002. Course Goals. Learn to use verification tools and experiment on actual designs used in industry Verisity Specman, IBM Rulebase Cadence NC-Sim VHDL simulation framework

lalasa
Download Presentation

Teaching Functional Verification – Course Organization

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Teaching Functional Verification – Course Organization Design Automation Conference Sunday, June 9, 2002

  2. Course Goals • Learn to use verification tools and experiment on actual designs used in industry • Verisity Specman, IBM Rulebase • Cadence NC-Sim VHDL simulation framework • Learn to plan and carry out effective functional verification of a design • Learn to work in teams to debug designs

  3. Desired Outcome • By the end of the course the student will • Have verified three example designs provided by IBM • Have an understanding of why verification is important • Have an understanding of the complexity of verifying modern computer systems

  4. Grading • Grade breakdown (Used at Penn State) • Midterm Exam: 20% • Final Exam: 20% • Verification Projects (~4): 45% (3 Calc Labs + 1 ruleBase) • Homework (~3): 15% (VHDL Background Check; e coding; rulebase) • Exams replaced with lab-oriented grading at UPitt • Final Exam was lab-based at Penn State

  5. Prerequisites • Hardware description language • VHDL or Verilog (MANDATORY) • Use of modern EDA tools • simulation, synthesis, validation (Synopsys) • schematic capture tools (LogicWorks) • Logic design/Computer architecture • logical minimization, FSMs, component design, pipelining, ISA design

  6. Prerequisites - Instructors • Find a good T.A. • Familiar with HDL;willing to explore tools • Tools: Licensing Information • Interfaced Specman with Mentor Graphics (Pitt, NC State) and Cadence tools (Penn State) • Quick Start • Specman - CPU tutorial; ebasics slides • Rulebase – Buffer tutorial

  7. Course Textbook/Notes • Janick’s textbook was used • Pitt and Penn State –“e based” • Covered first 3 chapters • Relied on Specman/Verification Advisor • IBM slides for rulebase • NCState –“VHDL based” • Supplemented with VHDL reference books

  8. Course Outline – Penn State Week 1: What is verification? (Chapt 1 of Janick's book; industry perspective) Week 2: Behavioral VHDL - refresher and writing testbenches – HW1 (VHDL) Week 3: Verification tools; Coverage metrics (Chap 2 of Janick’s book) Week 4: Behind the simulation engine – event and cycle simulation Week 5: Introduction to Specman and e language basics – (ebasics slides) – HW2 (e basics) Week 6: Lab 1 introduction/Specman – CPU tutorial Week 7: Verification plan – strategies/testcases/testbenches (Chap 3; VA) Week 8: Lab 1 solution discussion + Lab 2 introduction + Exam 1 Week 9: More e language constructs Week 10: Modeling structs;I/O blocks; data items– (VA) Week 11: Lab 2 Solutions and Lab 3 discussion Week 12: Modeling input relations/intervals/events – (VA) Week 13: Lab 3 solutions + Introduction to Formal Verification + Lab 4 Week 14: Introduction to Rulebase/ Rulebase lab Week 15: Exam review

  9. Course Outline – Pittsburgh Week 1: What is verification? (Chapt 1 of Janick's book; industry perspective) Week 2: Hardware Functional Verification; review of Modelsim Week 3: Verification tools; Coverage metrics (Chap 2 of Janick’s book) Week 4: Behind the simulation engine – event and cycle simulation Week 5: Introduction to Specman and e language basics – Verisity Tutorial Week 6: Calc 1 Lab Week 7: Verification plan – strategies/testcases/testbenches (Chap 3; VA) Week 8: Calc 1 solution discussion + Calc 2 introduction Week 9: More e language constructs Week 10: Modeling structs;I/O blocks; data items– (VA) Week 11: Calc 2 Solutions and Calc 3 discussion Week 12: Modeling input relations/intervals/events – (VA) Week 13: Calc 3 solutions + Introduction to Formal Verification + Lab 4 Week 14: Introduction to Rulebase/ Rulebase lab Week 15: Rulebase lab

  10. Course Outline – NC State Lectures 1-2 What is Verification? Chapter 1 Lecture 3 Verification Tools Chapter 2 Lectures 4-6 Verification Plan – Strategies/Testcases/Testbenches Chapter 3 Lectures 7-11 Architecting Testbenches Chapter 6 Lecture 12 Lab 1 Solution Discussion / Architecting Testbenches Chapter 6 Lecture 13 EXAM #1 – Chapters 1,2,3,6 Lecture 14 Lab 2 Overview / Stimulus and Response Chapter 5 Lecture 15 Review EXAM #1 Lectures 16-19 Stimulus and Response Chapter 5 Lectures 20,26 Special Topic Day - Online NetSeminar on new verification technologies Lecture 21 Lab 2 Solution Discussion Lectures 22-23 Behavioral HDL Chapter 4 Lecture 24 Lab 3 Overview / Behavioral HDL Chapter 4 Lecture 25 Simulation Management Chapter 7 Lecture 27 EXAM #2 – Chapters 5,4,7 Chapter 6 Lecture 28 Lab Day 

  11. Student Feedback • More quizzes/homework on “e” language • More time with labs especially “lab 3” • Work in groups on labs • Start earlier with Specman/e • Access to VA • Appreciate change from VHDL testbench to Specman environment (when doing lab 1 in dual form) • Appreciate change to Rulebase from Specman • Labs were most interesting part • More time with Rulebase

More Related