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Test Challenges for SiP

Test Challenges for SiP. Bill Price BAST 2002 06Feb02. -Bio-. BSEE Cal Poly, MSEE Univ. of Santa Clara Started in late ’60’s @ Fairchild Semi Philips (ex Signetics (ex Scientific Micro Systems)) since early ’70’s Wide variety of technical mgmt positions Design Engineering

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Test Challenges for SiP

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  1. Test Challenges for SiP Bill Price BAST 2002 06Feb02

  2. -Bio- • BSEE Cal Poly, MSEE Univ. of Santa Clara • Started in late ’60’s @ Fairchild Semi • Philips (ex Signetics (ex Scientific Micro Systems)) since early ’70’s • Wide variety of technical mgmt positions • Design Engineering • Operations (Product/Test Engr, Logictics, QRA) • CAD/IT • Currently part of CTO, focusing on issues related to Assembly/Test and new technologies • Biggest Challenge: building “bridges” between the vertical silo’s common in large multinational companies • Northern California native

  3. SOC: Limitations of Technology • Process Options are expensive, a compromise, and often too late… • Logic, Flash, DRAM, Analog/Mixed Signal, RF..impractical on one die? • Multi-chip packaging technologies making rapid advancements • Bump technologies: flip chip and face to face die stacking • Wire bonded die stacking: silicon spacers for same size die • Die Thinning: 3 die stacked in 1mm thick package??

  4. One Product=One Package+One Die Remember when life used to be simple?? If you can imagine it, someone can probably build it for you!

  5. SiP: multiple die in a package are here!-prepare for the challenges- • Finding all the pieces: Logic, Memory, RF, Analog, Passive Integration…. • Known Good Die: Are they available? Are they cost effective? • Debug/Failure Analysis: Plan ahead!! Design for Debug? • The Value Proposition: space, performance, power?? • Optimization Opportunities…Memory Width, Special I/O, ESD, etc. • Test Strategy: “making do” with what you can buy outside

  6. Example: SiP with P1500 test strategy ????? Testability “shell” “main die” w/on-chip cores 2nd Die

  7. Manufacturing Strategies?? • What happens to tests like IDDQ, VLV, etc??? • Test/Burn-in of partially completed packages?? • For example multiple memory die • Redundancy/Repairability?? • Implications for ATE Suppliers?? • All technologies now possible in one package?

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