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Xilinx CPLDs Low Cost Solutions At All Voltages

Xilinx CPLDs Low Cost Solutions At All Voltages. CPLD Product Portfolio Complete Solutions for all Markets. XC9500 5.0V 5.0 ns t PD 288 mcells. 0.50u. Lowest Cost 3.3V. XC9500XL 3.3V 5.0 ns t PD 288 mcells. XPLA3 3.3V 5.0 ns t PD 512 mcells. 0.35u. XC9500XV 2.5V 5.0 ns t PD

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Xilinx CPLDs Low Cost Solutions At All Voltages

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  1. Xilinx CPLDsLow Cost Solutions At All Voltages

  2. CPLD Product PortfolioComplete Solutions for all Markets XC9500 5.0V 5.0 ns tPD 288 mcells 0.50u Lowest Cost 3.3V XC9500XL 3.3V 5.0 ns tPD 288 mcells XPLA3 3.3V 5.0 ns tPD 512 mcells 0.35u XC9500XV 2.5V 5.0 ns tPD 288 mcells Low Power 0.25u Lowest Cost 1.8V CoolRunner-II 1.8V 3.0 ns tPD 512 mcells 0.18u Lowest Power

  3. Xilinx CPLD Feature Comparison Feature CoolRunner-II 9500XL / XV CoolRunner XPLA3 Core Voltage 1.8 3.3 3.3 / 2.5 Low Power RealDigital + DataGATE Low power mode RealDigital Global Clock 3 4 3 P-Term Inputs 40 40 54 Divide, DualEDGE & Clock Management None None CoolCLOCK LVTTL, LVCMOS, I/O Standards LVTTL, LVCMOS LVTTL, LVCMOS HSTL, SSTL I/O Banks 1 to 4 1 1 to 4 (XV) , 1 (XL) Macrocells 32-512 32-512 36-288 TPD / FMAX 3.5 / 333 5 / 200 4.0 / 250 Security Multiple levels 1 level 1 level Process Technology 0.18u 0.35u 0.35u / 0.25u

  4. The RealDigital CPLD A New Class of CPLD: High Performance & Ultra Low Power

  5. The RealDigital CPLD Advantage

  6. CoolRunner-II Family Overview

  7. CoolRunner-II Flexibility XC2C32 XC2C64 XC2C128 XC2C256 XC2C384 XC2C512 1 1 2 2 4 4 I/O Banks LVTTL33, LVCMOS       33, 25, 18, 15* SSTL3-1(3.3v), SSTL2-1 (2.5v), HSTL1 (1.5v)           Input hysteresis control       Slew rate control     CoolCLOCK     DataGATE       DualEDGE     Clock divider       Bus hold output       Hot pluggable       Programmable Grounds Note: 1.5v inputs need hysteresis

  8. Design Kit • A complete design kit for: • Logic designers new to CPLDs • CPLD designers new to Xilinx • ASIC designers • Simple, inexpensive demo board • Battery or AC outlet power source • Parallel printer cable for programming • LED's for simple testing • Dual in line I/O header for easy connections • Jumpers for easy modifications • Multiple device selection on a singleboard (CoolRunner-II or XC9500XL)

  9. Quick Start Training • All materials now released! • Full day of training at recent FAE conference • World-wide roll out complete • Set up your customer training now

  10. Quick Start Modules Get up to speed on CoolRunner-II features and new applications Module 1: CoolRunner-II Technology & Architecture Module 2: CoolRunner-II Advanced Features - I Module 3: CoolRunner-II Advanced Features – II Module 4: CoolRunner-II In Cell Phone Security Module 5: Cell Phone Handsets Module 6: CoolRunner-II in PDAs Module 7: DDR SDRAM Memory Interface Module 8: PicoBlaze CPLD Microcontroller Module 9: Powering CoolRunner-II CPLDs Module 10: Compact Flash for CoolRunner-II CPLDs Module 11: CoolRunner-II CPLDs in Security Module 12: XPower for CoolRunner XPLA3 CPLDs Module 13: XPower for CoolRunner-II CPLDs Module 14: CoolRunner-II Low Cost Solutions Module 15: Digital Camera Design Module 16: Low Power Memory Module 17: Smart Card Reader Module 18: CryptoBlaze

  11. Quick Start Modules at: http://www.xilinx.com/products/cpldsolutions/quickstart.htm

  12. The CoolRunner XPLA3 CPLD Family Low Power and 3.3V Operation

  13. CoolRunner XPLA3 - The Lowest Power 3.3V CPLD Solution • Low power, high performance CPLD • 5V tolerant I/O • <100uA standby power • Full JTAG compliance • Industrial temp grade operates from 2.7V • Ultra-small chip scale packaging • Perfect for portable applications • Robust architecture delivers great ISP • Superior pin-locking • WebPACK & ISE software support

  14. The XC9500XL CPLD High Performance and 3.3V Operation

  15. XC9500XL Key Features • I/O Flexibility • XL: 5v tolerant; direct interface to 3.3v & 2.5v • Input hysteresis on all pins for improved signal integrity • Easy ATE integration for ISP & JTAG • Fast, concurrent programming times • 36 to 288 macrocell densities • Complete IEEE 1149.1 JTAG • Space-efficient chip scale packaging

  16. t ( ns) XC9500XV 4 5 5 6 pd Registers 36 72 144 288 f XC9500XL 178 178 178 125 SYSTEM XC9500XV 200 178 178 151 Packages PC44 PC44 CS48 CS48 VQ44* VQ44* VQ64 VQ64 TQ100 TQ100 TQ144 TQ144 CS144 PQ208 BG256 FG256* CS280* XC9500XL Family XC9536XL XC95144XL XC9572XL XC95288XL Macrocells 36 72 144 288 Usable Gates 800 1600 3200 6400 t ( ns) XC9500XL 5 5 5 7.5 pd

  17. Cost= Design + Product Cost + COS = Value Product Innovation Inventory Sort Assembly Final Test Programming Distribution Wafer P W S T I P D A Customer Aggressive Cost Management It’s More Than Just Process and Product Technology Innovation

  18. The Complete CPLD Solution • 1.8 volts to 5 volt operation • Low power/high performance • Low cost

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