Topics

1. Topics • Review of VHDL • Discussion of simulation test methods • Advantages of HDL-based design • Discussion of current design methodologies • Presentation of an example design using VHDL

2. What is VHDL? • VHDL is a Hardware Description Language used to capture the design in a technology independent medium. • The VHDL design is targeted to the FGPA or ASIC through synthesis. RTL VHDL SYNTHESIS FPGA

3. What is VHDL? (2) • VHDL is also a high-level language used to simulation test a device. TESTBENCH VHDL The testbench is written in “behavioral VHDL”. The design is written in “RTL VHDL”.

4. Simulation Test Methods Stimulus Design Non-portable DESIGN (SCHEMATIC OR OTHER) SIMULATOR STIMULUS COMMANDS Simple BEHAVIORAL TESTBENCH RTL VHDL Complex BEHAVIORAL TESTBENCH RTL VHDL

5. Modern Design Methodology Using HDL’s START CODE VHDL BLOCK SYNTHESIS SIMULATION TEST BLOCK VENDOR PLACE & ROUTE BLOCKS DONE? STATIC TIMING ANALYSIS no yes TIMING SIMULATION SYSTEM-LEVEL SIMULATION

6. Advantages of HDL-Based Design • Technology independence • Re-use of Intellectual Property • Advantages of high-level language design

7. Technology Independence • Vendor independence through synthesis RTL VHDL OPTIMIZE MAP TO BOOLEAN OPTIMIZE LIBRARY CONSTRAINTS MAP TO TARGET TECHNOLOGY GATE-LEVEL NETLIST $ Allows vendor decisions to be based upon both cost and technology

8. Technology Independence (2) • Allows for FPGA to ASIC, and FPGA to FPGA retargetting simply by re-synthesizing $ Not having to recapture the design saves substantial time. $ Masked gate arrays can cost substantially less than FPGAs for high-volume applications.

9. High-Level Language Design • Easier design entry(count <= count + 1) $ Faster design is faster time to market • Use of high-level language for simulation test • pseudo-code stimulus • file I/O for regression testing, etc. • dynamic protocol checking • timing checks $ Debug is more effective during simulation than in the lab due to visibility.

10. Re-use of Intellectual Property • Applicable for both stimulus (BFM’s) and RTL (the design) • Complex functions: • bus interfaces • memory controllers • proprietary blocks • purchased IP • Simple functions: • decoders • parity generators • readback muxes • Advanced VHDL features for IP creation (GENERATE, GENERIC) $ Long term savings

11. Current Methodologies in Use • A mixture of AHDL, schematics, and proprietary vendor tools • Vendor specific • Difficulties applying multiple engineers $ Can’t take advantage of technology advances from different vendors $ Being tied into one vendor eliminates the “playing card” for the supply chain

12. Current Methodologies (2) SIMULATOR STIMULUS COMMANDS FPGA • Test method • Single device test • Stimulus method proprietary • Little or no protocol/timing checks • No modeling of purchased components $ Longer debug time

13. An Example Design- A Marine Radar Tracker/Detector EXTERNAL SRAM RMW SRAM CONTROLLER BEAM VIDEO PULSE RULES BEAM RULES RANGE BUS INTERFACE AUTO ACQUIRE ACQ MEM WIDTH SUM TRACKER TRACK MEM MOMENT TRACK WINDOW MEM

14. Example Design - Simulation Testbench VIDEO GENERATOR TARGET TRACKER DETECTOR FPGA SRAM PROCESSOR BFM (68K) -- normalize start and end test */ starttest := starttest - 1; endtest := endtest - 1; currenttest := starttest; -- Put CW2 in TRAINING mode write(CW2_REG, CONV_SLV(INTERN_DSYNC,16), cyc); -- Set errors to 0 err.errors := 0; -- perform all desired tests do_all_tests : WHILE currenttest <= endtest and err.errors = 0 LOOP write(linedata, STRING'("Starting test #")); write(linedata,currenttest+1); writeline(output,linedata); err.test := currenttest; tst_ctrl(tib(currenttest), err, ret_data, cyc); currenttest := currenttest + 1; END LOOP do_all_tests;