המעבדה למערכות ספרתיות מהירות

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Full sniffer system for PCIe Midterm presentation Performed by: Omer Blecher , Roy Fridman Instructor: Boaz Mizrachi

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Agenda • Main Goal and Project A Goals • Current status • System characterization • Long Range modifications • First step modifications • completed tasks • Future tasks and current semester plan

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Main Goal • Providing a fully operational Sniffer who is able to connect on a PCIe bus ,stream a PCIe packet to a analyzer and perform a complete packet analysis of the signals in an analysis and control PC . • General purpose of project utilizing/modifying existing components of the system and creating missing components for (full system integration).

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Project A goals(1/2) • Gaining extensive theoretical knowledge of the systems current building blocks. • Learning the platforms/protocols and algorithms needed on a wide perspective – • PCI express electrical definitions and protocol requirements. • 8/10 bit coding. • UART connection. • RocketIO transceivers. • s/w and h/w platform design tools such as PPC,HDL designer, Xilinx platform studio.

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Project A goals(2/2) • Creating a fully detailed system characterization (h/w, s/w and more) including future s/w and hardware modification and algorithms that will be implemented on project B. • full system operation and “hello world” modification: • 1. Hardware: moving the TGA current design from the FF672 evaluation board to the FF1152 and confirming that the design is fully active on the new board (will be elaborated ). • 2. software: creating a flow that its main purpose is to display a packet (will be elaborated ).

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Current status (General) FF672 Crossbar Board Passive Trace Board PC Test Management cable 2.5G 2.5G cables

7. Start K char X X Stamp Stamp X X X End K char Time Depends on min and max parameters Data padding High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Current status (Hardware) • CTG – creates a burst of Randomized packet transmission with defined parameter of min and max values in the PGP BRAM. • CTA – received the sent burst after alignment, saves only the damaged packet in the TSS BRAM.

8. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Current status (Software) • Pic (microcontroller)- configure M21121- 34x34 Crosspoint switch , write and read data from the EEPROM , Turn on or off LEDs ,enable and disable dipswitches, read status bits from the card and write control bits • Power PC- turn on LEDs , read status of dipswitchesand push buttons, read and write from the TSS and PGP memories, and send command to the pic. • Experiment GUI- not relevant because it will be recreated to suit different needs

9. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System characterization (Top down) • Features and utilization in S/W: • Displaying packets in logical sectors • Traffic Summary • Link Tracker • Timing calculations • Bus utilization • Advanced Search for specific packets

10. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Displaying packets in logical sectors (1/5) • There are 4 PCIe transaction types: • Memory transaction. • I/O transaction. • Message transaction. • Configuration transaction. Memory Write Request Memory Read Request Memory Write Completion Memory Read Completion I/O Write Request I/O Read Request I/O Write Completion I/O Read Completion Interrupt signaling Error signaling Power management Configuration Write Request Configuration Read Request Configuration Write Completion Configuration Read Completion

11. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Displaying packets in logical sectors (2/5) Basic display method:

12. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Displaying packets in logical sectors (3/5) General: • Serial number: every packet gets a number which indicates the order of the arrival. • TLP: the sequence number which was given to the packet by the DLLP. • ECRC: Every packet can have ECRC- CRC calculation which created in the TLP. • LCRC: Every packet has a LCRC- CRC calculation which created in the DLLP. • Time stamp: Every packet gets a time stamp- indication of the arrival time.

13. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Displaying packets in logical sectors (4/5) Request Packets: • Type of transaction: Memory, I/O ,Configuration and Message. • Operation: Read or Write . • RequestID: The I.D number of the device which create the request. • Tag: Field to identify the request. • Byte Enable: Indicates which byte of the DWord is a valid data bytes, and which byte is “Padding” bytes. • Address: The register which we want to read/write from/to. • Data: The intended data (optional).

14. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Displaying packets in logical sectors (5/5) completion Packets: • Completion I.D: The I.D number of the device which send a complition. • Completion Status: Indication if the device perform a successful completion. • Byte Count: Indication of how many packets are left to complete memory read • request. • RequestID: The I.D number of the device which create the request. • Tag: Field to identify the origin of the request • Low Address: Byte address of the first enabled byte of data.

15. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Traffic Summary (1/2) The s/w will consist of 5 detailed summeries: • General packet summery: Show a summery of of all packets • Group by valid and invalid packets. • TLP packet summery: Show a summary of all the packets that • origin from the TLP, group by all type of TLP types. • Request summery: Show a summery of all the request packets, group by the different • requester I.D. • Completion summery: Show a summery of all the completion packets, group by the • different completer I.D. • Error summery: Show a summery of all the damaged packets, group by all types of • error.

16. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Traffic Summary (2/2) Display method of 2 root summaries:

17. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Link Tracker (1/2) • Presenting the arrival of packets according to a time table: • The first column is for the time since the beginning of sampling packets. • The second column shows the number of packet. • The third column shows packets that arrive from the graphic card. • The forth column shows packets that arrive from the mother-board.

18. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Link Tracker (2/2) Basic display method:

19. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Timing calculations • Calculate efficient bus width in an interval of time • Choosing the start time of the calculation: • Choosing the end time of calculation: • Presenting the total time: • Presenting the bit rate of the upstream and the bit rate of the down stream: • *** Time is measured between different intervals that will be defined by the user.

20. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Bus utilization Presenting a diagram of number of packets every 1 micro second:

21. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Advanced Search for specific packets (1/2) • Configure the analyzer to capture a specific range of packets: • The configuration is made by sending a mask to themodified TGA: The mask contain a sequence of bits for h/w filtering use. the main idea is that the user defines a search and a mask is created accordingly in the PC. A predefined h/w block added o the TGA will use the mask to filter wanted packets. • Search display method: after the receiving of the packets, we will show on the screen only chosen packet or range of packets.

22. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Advanced Search for specific packets (2/2) STP (K27.7) R|Fmt|Type Continuation of the header Sequence Number The chosen byte (first byte of the header) R|Fmt|Type 000 11111 Type Configuration 00100 I/O Request 00010

23. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Long range modifications • Classifier – A component with basic logic abilities of receiving a word of 32 bits (A) and compare a selected stream of bits in A to a known “mask” (B) and perform the following logic operations: • A=B? A<B? A>B? A<>B? • DRAM controller+buffer - interface with DRAM is needed for minimizing trade off problem with quality of filtering and allowing wanted features that are mapped in the system characterization.

24. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Software first step modification Start K char Time X X X End K char

25. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Hardware first step modification Full design relocation

26. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Completed tasks • System characterization - s/w and h/w • systems current building block extensive review • PCI express electrical definitions and protocol requirements. • 8/10 bit coding. • UART connection. • RocketIO transceivers.

27. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Future tasks and current semester plan • weekly minimal hourseach – • until 6/4/06: 36 • (3 days) • 2. After 6/4/06: 18 • (day and a half) Detailed distribution

28. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Detailed time distribution • S/W: • Design environment review (c++) 4 weeks • 2. Basic GUI creation 1 week • 3. System interface with FF672 and FF1152 2 week • 4.Integration (first step s/w modification) 1 week • H/W: • 1. Low level system designs 5 weeks • 2. first step h/w modification 3 weeks