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RMO4C-2

RMO4C-2. A Low-Noise 40-GS/s Continuous-Time Bandpass ΔΣ ADC Centered at 2 GHz Theo Chalvatzis and Sorin P. Voinigescu The Edward S. Rogers Sr. Department of Electrical and Computer Engineering University of Toronto Toronto, Canada. Outline. Motivation ADC system level architecture

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RMO4C-2

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  1. RMO4C-2 • A Low-Noise 40-GS/s • Continuous-Time Bandpass ΔΣ ADC • Centered at 2 GHz • Theo Chalvatzis and Sorin P. VoinigescuThe Edward S. Rogers Sr. • Department of Electrical and Computer Engineering • University of Toronto • Toronto, Canada

  2. Outline • Motivation • ADC system level architecture • Circuit design • Measurements • Conclusion RFIC - San Francisco June 11-13, 2006

  3. Motivation • Direct sampling receiver for 2-GHz CDMA basestation • Transistor fT of 150..250 GHz and low-BVCEO naturally point to 1-bit ΔΣ digitization of RF signal • Continuous-Time Bandpass ΔΣ topology offers: • Higher resolution and lower power than other ADC types • Low complexity (simple layout is important at 40 GHz!) • LNA as input stage RFIC - San Francisco June 11-13, 2006

  4. System Level Architecture BPF2 LNA & BPF1 • 2-GHz Gm-LC BPF • 1-bit quantizer as DFF • RZ pulse DACs • Loop design in s-domain DAC(s) the TF of RZ DAC RFIC - San Francisco June 11-13, 2006

  5. New Loop Filter Topology • MOS-HBT cascode provides: • Linearity and low-noise with no degeneration • Lower power supply (VGS<VBE) • Bias at peak-gm current density for maximum linearity LE for input 50Ω matching: LEE for common mode rejection RFIC - San Francisco June 11-13, 2006

  6. New RZ DAC Topology • DAC with RZ pulse for immunity against loop delay • Higher switching speed due to MOS-HBT cascode • High gm/ITAIL ratio (due to HBT) RFIC - San Francisco June 11-13, 2006

  7. New 40-GHz Quantizer Topology • MOS-HBT MSM flip-flop: • 3 latches to compensate for metastability • MOS on clock path to improve speed with low supply • HBT on data path for high gain Min swing at quantizer input: 10mVpp 3 stages needed for full logic swing (300mVpp) at DAC input RFIC - San Francisco June 11-13, 2006

  8. 40-GHz Bandwidth Clock Distribution • External clock distributed to 3 latches and 2 DACs • EF-MOS-HBT cascode for increased bandwidth and large capacitive load drive RFIC - San Francisco June 11-13, 2006

  9. Fabrication and Characterization of loop filter breakout and ADC RFIC - San Francisco June 11-13, 2006

  10. ADC Die Photograph • ADC and filter breakout fabricated in STM’s 0.13μm SiGe BiCMOS: • HBT fT/fmax=150/160 GHz • 2μm finger width n-MOSFET fT/fmax=80/90 GHz • Total power dissipation 1.6W from 2.5V 1.52x1.58mm2 RFIC - San Francisco June 11-13, 2006

  11. Loop Filter – Measurements • Linearity and noise measured on a filter test structure • Optimum bias point for maximum linearity: 0.4mA/μm RFIC - San Francisco June 11-13, 2006

  12. ADC – S-parameters Single-ended measurements • Q=17 and BW3dB=120MHz • ADC stable up to 65GHz • S22<-7dB up to 65GHz and <-15dB up to 22GHz RFIC - San Francisco June 11-13, 2006

  13. ADC – Spectrum Measurements • No idle tones present in-band • Inset shows > 35dB/dec noise shaping Single-tone at 2-GHz ON Single-tone at 2-GHz OFF RFIC - San Francisco June 11-13, 2006

  14. ADC – SNDR Measurements • SNDR measured with Spectrum Analyzer • Resolution BW lowered until noise floor remained constant (RBW < 50 KHz) • Measurements taken for bandwidths between 1 MHz and 120 MHz RFIC - San Francisco June 11-13, 2006

  15. ADC – SNDR vs BW Measurements • SNDR=55dB over 60 MHz • SNDR=52dB over 120 MHz RFIC - San Francisco June 11-13, 2006

  16. ADC – SFDR Two-Tone Measurements • Two-tone test with 2 GHz RF inputs at 10 MHz spacing • PIN= -30dBm • SFDR=61dB RFIC - San Francisco June 11-13, 2006

  17. ADC – 40-Gb/s Eye Diagram Jitter Measurements • 2-GHz input sinusoid • Feedback turned-off • JitterRMS=375fs • Jitter does not affect ADC resolution RFIC - San Francisco June 11-13, 2006

  18. ADC Performance Figure of Merit (FOM) definition (lower better): RFIC - San Francisco June 11-13, 2006

  19. Conclusion • First mm-wave sampling ΔΣ ADC in any technology (> 2xFs) • Direct RF A/D Conversion at 2-GHz with 9-bit resolution over 60 MHz • 11 bits over 60 MHz possible in this topology with: • Improved filter linearity • Higher filter Q • Best FOM among all ADCs with clocks > 1 GHz • 40-48 GS/s design scalable to 3.5/5/12 GHz RFIC - San Francisco June 11-13, 2006

  20. Acknowledgements • Eric Gagnon and Morris Repeta for system performance specifications • Nortel Networks for funding support • STMicroelectronics for chip fabrication • ECTI for lab access • CMC for CAD tools RFIC - San Francisco June 11-13, 2006

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