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Synthesis for Test

Synthesis for Test. Virendra Singh Indian Institute of Science Bangalore virendra@computer.org. IEP on Digital System Synthesis @ IIT Kanpur. Testability. Objective Improve Controllability Observability Reduction in sequential depth Elimination of sequential loop.

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Synthesis for Test

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  1. Synthesisfor Test Virendra Singh Indian Institute of Science Bangalore virendra@computer.org IEP on Digital System Synthesis @ IIT Kanpur

  2. Testability • Objective • Improve • Controllability • Observability • Reduction in sequential depth • Elimination of sequential loop SfT@iitk

  3. Sequential Depth Reduction - Allocation • Allocation Scheme • Enhance controllability and observability • Reduction in Sequential depth Based on RT Architecture Independent of Test Technology SfT@iitk

  4. Controllability and Observability a Allocation 1 R1: a, c, g R2: b, d, h R3: e R4: f b c d e f g h Lifetime table SfT@iitk

  5. Controllability and Observability a Allocation 2 R1: a, c, R2: b, d R3: e, f R4: f, g b c d e f g h Lifetime table SfT@iitk

  6. Controllability and Observability If any one of variable assigned to a register is a PI (PO) of the chip, this register is directly controlled (observed); if not, register can be accessed through other registers Goal: To ensure that as many registers as possible in the implementation are assigned at least PI/PO Each row of register must cover a PI/PO TSR1: Whenever possible , allocate a register to at least one PI or PO SfT@iitk

  7. Sequential Depth Reduction a b d e 0 a b +2 +1 c 1 d c f +3 e 2 f g g SDFG Lifetime Table SfT@iitk

  8. Sequential Depth Reduction TSR1 does not provide inform testability suggestions on module allocation and interconnect allocation Register allocation using TSR1 R = { (a,c,g), (b,f), (d), (e)} Two possible Module allocation M1 ={(+1,3), (+2)} M2 ={(+1,2), (+3)} SfT@iitk

  9. Sequential Depth Reduction • M1 is preferred to save interconnect cost • output of +2 is hard to observe • An error effect needs to propagate through an additional register R2 before it can be observed SfT@iitk

  10. Sequential Depth Reduction d a b R3 R = { (a,f,g), (b,c), (d), (e)} R1 R2 R4 g e TSR2: Reduce the sequential depth from an input register to an output register SfT@iitk

  11. Sequential Depth Reduction a b R = { (a,c,g), (b,f), (d), (e)} R1 R2 d R3 g R4 e SfT@iitk

  12. Sequential Loop Reduction 1 R1(a) +1 R2 2 R2(b) +2 R1 3 R3(c) +3 4 R3 R1(d) Sequential Loop: Reuse of R1 SDFG SfT@iitk

  13. Sequential Loop Reduction x2 x9 x1 +6 6 +7 +8 +1 TIME 1 e a +2 f TIME 2 b g +3 TIME 3 c +4 TIME 4 d +5 TIME 5 y SfT@iitk

  14. Sequential Loop Reduction SfT@iitk

  15. Sequential Loop Reduction A1 R1 R4 R2 R3 R5 SfT@iitk

  16. Sequential Loop Reduction A2 R1 R4 R2 R3 R5 SfT@iitk

  17. Scheduling for Sequential Depth/Loop Reduction • TSR3: Reduce Sequential loop by • Proper resource sharing to avoid creating sequential loops for cyclic DFG • Assign IO registers to break sequential loop • TSR4: Schedule operations to support the application of TSR1, TSR2, and TSR3 SfT@iitk

  18. Controllability Primary input a Primary input 0 R(a) 0 + + * R(b) 1 1 R(b) - * - 2 R(c) 2 R(c) R = (b,c, …) Not directly controllable R = (a,b,c, …) Directly controllable SfT@iitk

  19. t R1(w) t R1(w) + * + t+1 t+1 * R1(x) - R1(x) R1(y) R2(y) - t+2 t+2 * t+3 * R1(z) t+3 Observability R2(z) R1 = (….,w,x, …) Not directly observable SfT@iitk

  20. t R1(w) *1 t+1 R2(v) R3(s) R1(x) *2 - t+2 R3(u) R2(y) + t+3 R2(z) Sequential Depth Reduction t R1(w) R2(v) *2 *1 t+1 R3(s) R1(x) R2(y) - t+2 R3(u) + t+3 R2(z) SfT@iitk

  21. Mobility Path 1 2 * 6 * * 8 + 10 * TIME 1 * 7 * + 9 < 3 11 TIME 2 - 4 TIME 3 - 5 TIME 4 SfT@iitk

  22. Mobility Path + * * TIME 1 - * TIME 2 - TIME 3 TIME 4 SfT@iitk

  23. Mobility Path Scheduling • Mobility_path_scheduling(G){ • ASAP_scheduling(G); • ALAP_scheduling(G); • Update_op_slack_and_mobility(G); • While (unscheduled_op(G) ≠ 0){ • Pk = next_min_mobility_path(G); • partial scheduling(Pk, G); • testMP(Pk, G); /analyze testability on Pk • } • } SfT@iitk

  24. Mobility Path Scheduling • partial_scheduling(Pk,G){ • For each (operation o on Pk) • if (o.earliest = o.latest) // mobility becomes 0 • o.active = o.earliest // assign schedule • Update_op_slack_and)mobility(G); • While (unscheduled_op (Pk) ≠ 0){ • (o, o.ll_cycles) = next_op_with _least_no_light_load_cycles(Pk, G); • o.active = most_preferred_cycle(o.ll_cycles, G); SfT@iitk

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