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NSLS-II Power Supply Control System

NSLS-II Power Supply Control System. Yuke Tian Accelerator Division Photon Science Directory Brookhaven National Lab. Outline. 1. NSLS-II power supply control system System Overview  Three types of PS operation mode  PS control data flow

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NSLS-II Power Supply Control System

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  1. NSLS-II Power Supply Control System Yuke Tian Accelerator Division Photon Science Directory Brookhaven National Lab

  2. Outline 1. NSLS-II power supply control system System Overview  Three types of PS operation mode  PS control data flow 2. Application software and EPICS device support Engineer test screen Public PV lists and database Device support 3. Generic IOC-FPGA communication protocol  Move data bwteen EPICS IOC and FPGA device  Genetic IOC-FPGA communication protocol 4. Hardware level

  3. System Overview Magnets and Power Supplies in Storage Ring

  4. What are the common features for power supply control ? 1. Control magnet current through power supply with high accuracy (a few ppm) Static: slow power supply setpoint change (a few Hz)  EPICS IOC to power supply controller. Ramping: ramping power supply through pre-defined ramping function (10KHz-100KHz for a few seconds)  Need ways to download ramping function; need memory to save it. Feedback: power supply setpoint is calculated from feedback system (a few Hz to 100KHz depending feedback loop rate)  Need ways to send the feedback results to power supply controller in a deterministic way. 2. To synchronize magnets behavior  Need interface to timing system 3. A lot of power supply/magnets diagnostic data:  Need a lot of ADCs, digital inputs/outputs  Need a large memory to save the diagnostic data

  5. Let’s build a power supply control system EPICS IOC TCP/IP Triggers from timing system FPGA Large memory (DDR2/DDR3) Deterministic link to FOFB Fiber Magnet FPGA High precision DAC (20-bit) Power Amp DCCT Many ADCs (16-bit)

  6. Let’s build a digital power supply control system EPICS IOC TCP/IP Triggers from timing system FPGA Large memory (DDR2/DDR3) Deterministic link to FOFB Fiber Magnet FPGA Power Amp Digital regulator DCCT Many ADCs (16-bit) High precision ADC

  7. Real NSLS-II power supply control system

  8. NSLS-II PS control operation modes

  9. PS Control Data Flow High Level Applications CA EPICS IOC EPICS-FPGA Protocol FPGA embedded microBlaze PLB PLB PLB Registers DDR2 Memory PS SDI Link PSC Fiber TX/RX Controller logic(verilog) Fiber link (50Mbps) PSI Fiber TX/RX Controller logic(verilog) 8 Digital Outputs (static/pulse) 16 Digital Inputs (10ns sequence detector) 18 ADCs (16bit, 100KHz) 2 DACs (20bit/100KHz) logic(verilog) logic(verilog) logic(verilog) logic(verilog)

  10. Engineer Test EDM Screen – Ramping PS Example Digital output data Analog output data Digital /analog input data 9 ADC waveform 9 ADC waveform

  11. Engineer Test EDM Screen – Ramping PS Example ADC channel selection Ramping marker (also shown on oscilloscope) 1.1 second ADC waveform (10KHz)

  12. Engineer Test EDM Screen – ADC Noise Measurement ADC readback (single channel chip) Peak-peak: 1mv (LSB=0.3mV) ADC readback (6channel chip) Peak-peak: 2mv (LSB=0.3mV)

  13. Device Support and Start Up Script

  14. Move Data Between EPICS IOC and FPGA Device CA Client (Physics applications) Channel Access EPICS IOC Small Data BulkRx Data BulkTx Data (ai,ao,di,do etc) BPM: gain, calbration BPM: filter coefficients BPM: TBT, ADC raw CC: matrix selection CC: reverse response matrix CC: 10KHz orbit data PSC: setpoints, commands PSC: Booster ramping function PSC: ADC readbacks TCP/IP FPGA (microBlaze / Xilkernel / LWIP TCP/IP) DDR2/DDR3 MPMC registers BRAM How do we design a simple/reliable protocol to transfer data between IOC /FPGA quickly ?

  15. General IOC-FPGA Communication Protocol EPICS IOC Small Data BulkRx Data BulkTx Data (ai,ao,di,do etc) Out: Combined small data into one MTU by using aSub. In: parse one MTU into small data. Asyn Record Asyn Record Large amount data ID frame ID frame (optional) Large amount data 1MTU (10Hz) 1MTU (10Hz) asyn port 1: drvAsynIPPortConfigure (“NormalRxTx", "192.168.1.10:7 TCP",0,0,0) asyn port 2: drvAsynIPPortConfigure (“BulkRx", "192.168.1.10:18 TCP",0,0,0) asyn port 3: drvAsynIPPortConfigure (“BulkTx", "192.168.1.10:20 TCP",0,0,0)

  16. Hardware Level – PSC

  17. Hardware Level – PSC 3 6 4 1 7 7a 8a 5 2 8b 1 = JTAG connectors – Programming to FPGA and CPLD. 2 = RS232 port – Communication to PC for diagnostic and software development. 3 = DDR2 memory modules – PS diagnostic data, CPU memory. 4 = SDI connectors – Communication between PSC master (or cell controller) and PSC slaves. 5 = Fiber transceiver – Communication with PSI. 6 = Ethernet connector – Communication to EPICS IOC for PSC master. 7 = FPGA (Spartan3A) 8 = CPLD(8a) & SPI memory(8b) – Dual boot and remote programming functions.

  18. Hardware Level – PSC and Switch Brocade FWS624 24-port Switch (4 GigE + 20 10/100Mbps) GigE to Linux IOC’s private network card PSC chassis and 20 PSCs

  19. Hardware Level – PSI

  20. Hardware Level – PSI Fiber to PSC 2 DACs (20bit, 1ppm resolution, 1ppm linearity, 0.1ppm/C drift)

  21. NSLS-II power supply control system Want it ? You got it. NSLS-II power supply control system is a open source hardware.

  22. Summary 1. Accelerator power supply control is the common task for each laboratory. It has similar requirements, and thus the similar architectures. 2. NSLS-II power supply control system design is based on the experiences from both power supply group and control group. 3. All the NSLS-II power supply control hardwires are in production stage. FPGA firmware and EPICS driver/applications are being tested on Booster and storage ring magnets. 4. NSLS-II power supply control system is a open source hardware. The PCB design, FPGA firmware design, and the EPICS driver/application design are open to the community.

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