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ECS-TELL upgrade @ CBPF/LHCb. Express of Intention to contribute onto ECS development of the Upgrade of TELL module in CBPF/Brasil. our understanding status, discuss directions. the institute & people. André Massafferri Centro Brasileiro de Pesquisas Físicas.
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ECS-TELL upgrade @ CBPF/LHCb Express of Intention to contribute onto ECS development of the Upgrade of TELL module in CBPF/Brasil our understanding status, discuss directions the institute & people André Massafferri Centro Brasileiro de Pesquisas Físicas mostly based on feedback from Guido and Beat Fermilab + LHCb (Muon & Physics) ... maybe not on Eletronics @ LHCb massafferri@cbpf.br
The CBPF (1949) www.cbpf.br Centro Brasileiro de Pesquisas Físicas Rio de Janeiro / Brasil pmeson discovery Lattes,Ochialini,Powell (1947) Feynmann (50’s) QFT others Experimental & theory pos-graduation reference in Latin America • LNCC (scientific computing LAB) • IMPA (pure math) • LNLS (syncrotron light LAB) HEP, cosmology, solid, nuclear, theory, phenomenology, … were born @ cbpf • 15 LABs • brandy new one (large) for HEP research coupled to one of Electronics http://portal.cbpf.br/index.php?page=tecnologia.labs
High Energy Physics in CBPF 80’s: Charm Physics Program – Fixed Target - Fermilab Physics: mostly 3-body hadronic decays Advanced Computing Processor (parallel arch) e691, e769, e791, e831 Reconstruction & stripping • new concept: Topological HLT • gas gain uniformity test MWPC • Front-End Amplifier Muon System (2001) e831 Join to UFRJ ASICs design Test system Daniele, Werner Rafael Possible collaboration new Tracking Nakada @ CBPF
High Energy Physics in CBPF D S Q4 Q3 Q2 Q2 S Q3 Q4 33 59 57 23 0 23 33 80’s: Charm Physics Program – Fixed Target - Fermilab Physics: mostly 3-body hadronic decays Advanced Computing Processor (parallel arch) e691, e769, e791, e831 Reconstruction & stripping • new concept: Topological HLT • gas gain uniformity test MWPC • Front-End Amplifier (1995) e831 Forward Proton Detector @ D0 (Run II) meters
High Energy Physics in CBPF 90’s: Cosmics detectors Auger Observatory South site Argentina 00’s: GRID ROC Latin America 00’s: also neutrinos produced from nuclear reactor First stage of a long term neutrino’s oscillation experiment
Muon SW offline INFN: MWPC Muon Test system André Massafferri: researcher ECS & CBPF since 2009 (eng) Rafael Nobrega: fellow INFN: ECS Muon System FEB working @ CERN full support from our agencies: people, instrumentation, travel • 2008 – CBPF interest to participate on upgrade • Feb 2009 – conversation with Guido @CERN possible ECS contribution onto the new module: still to be defined by Beat Jost ex (Herman) DataProc (phys) Pablo Diniz: technologist [Phd Berlin, DSP, semiconductors] (tech) Fernando Sousa: master student gradually (eng) Herman Lima: technologist [FPGA] (eng) Leonardo Lessa: master student [1 year CMS computing] (phys) Irina Nasteva: posdoc [5 years UK, C++ & NEMO] • now – ready to collaborate onto the development of ECS-TELL upgrade
TELL1 upgrade: possible arquiteture (among many) TELL1 TELL-upgrade: arch very different (L0) Guido scheme 3 PHASEs 1. ECS unit 3. phys. frame: PCB + MEZZANINO + PWR 2.TopAlgo possible starting point for CBPF
1. ECS unit Fernando: output communications Rafael: Arria II & PCIe (tool as JUNGO) • same arch + different technology Lessa: definitive (low level) driver • short term tasks inside group Irina: Top Algo of ECS-TELL1 • Test this unit on TELL1 if possible mother Gluecard interface FPGA CCPC JTag Top Algorithm PCI ETHERNET I2C parallel Control room / PVSS extra I/O Upgrade: SMA200-Intel PCIe Arria II-Altera
ECS unit Beat scheme JTag ethernet Arria II SMA200 CCPC I2C
ECS unit: • Development using evaluation boards evaluationboard Arria @ CERN since June09 SMA200DK Arria II GX soon @CBPF 2x PCIe SMA200 CCPC 4x ethernet 4x 4x
ECS unit: • Development using evaluation boards SMA200DK Arria II GX soon @CBPF USB SMA200 ethernet JTAG PCIe &leds
ECS unit: • Development using evaluation boards SMA200DK Arria II GX Signal Tapping soon @CBPF • Output communication in FPGA: done for I2C Cyclone FPGA codefrom TELL1 site An alternative solution for Jungo driver; can be interesting if reliable move to use Altera IP blocks (free) • PCIe implementation on Arria FPGA using Jungo driver is evolving • Just started: • Dev of dedicated device driver + API • Study TopAlgo ECS-TELL1 FPGA USB PC using last compatible CSL kernel I P PCIe Jungodriver App JUNGO OK
Integration 1. ECS unit: 3. phys. frame: PCB + MEZZANINO + PWR 2. TopAlgo hearBeatplans (+ student) >> We are ready to continue developmentphase 1 >> We are @ disposal to collaboratephase 3 >> Wecankeeppeople @ CERN for fewmonths in middleof2010 to work ontest/adjustthe Prototype = phase 1 & 3 >> Alsowe are @ disposal to collaboratephase 2
Conclusion • We are ready to collaborate onto ECS of the next TELL module: man power • CBPF has been participating on HEP & instrumention: new lab • Full support from our agencies for R&D • and likely for mass production (local industry) • a TELL-upgrade workshop in Rio 2010 ?