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ヴァンデグラフでの回路図. A & T シグナル 回路図. LEMO-FLAT 5m x2. LEMO-LEMO 5m x32. Analog Delay 200ns. VME QDC V792. 16ch x2. 32ch. ECL Logic Delay 200ns. VME TDC V775. HIME. A. LEMO-LEMO 9m x88. FLAT-FLAT 1m x2. Splitter & att. VME Discri V895. T. 二股 FLAT-FLAT 1m x2. LEMO-LEMO
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A&Tシグナル 回路図 LEMO-FLAT 5m x2 LEMO-LEMO 5m x32 Analog Delay 200ns VME QDC V792 16ch x2 32ch ECL Logic Delay 200ns VME TDC V775 HIME A LEMO-LEMO 9m x88 FLAT-FLAT 1m x2 Splitter & att VME Discri V895 T 二股FLAT-FLAT 1m x2 LEMO-LEMO 5m x32 16ch x2 88ch 16ch x2 to trigger circuit 16ch x2 32ch LEMO BNC BNC - LEMO 変換 FLAT LEMO - BNC 変換
トリガーロジック 回路図 1. M1 2. M2 3. M3 4. Tcal VME discr V895 NIM Coin N-RS 413 V2 HIME L NIM Coin N-TM 103 NIM Coin N-TM 103 OR QDC V792 GATE GG F/F Delay START TDC V775 Discri sum Delay VME discr V895 Discri Delay multi out HIME R M2 GG (Latch) TKY-0240A Discri DAQ BUSY CLR Delay multi out F/F M3 START Tcal RIS-0300 Delay TEST IN VME discr V895 STOP
A&Tシグナル 回路図 BNC-BNC 12m x2 S.C. A LEMO-LEMO 5m x96 Splitter & att LEMO-FLAT 5m x6 Analog Delay VME QDC V792 T 2ch 16ch x6 32ch x3 LEMO-LEMO 2m x8 VETO BNC-BNC 9m x6 A LEMO-LEMO 0.2m x16 ECL Logic Delay VME TDC V775 Splitter & att NIM Discri NIM-ECL GNN-34DL T 16ch x1 FLAT-FLAT 1m x6 6ch 8ch 8ch to trigger circuit 特殊FLAT-FLAT 1m x1 HIME A LEMO-LEMO 9m x88 LEMO-LEMO 2m x88 Splitter & att CAMAC Discri 3412 T FLAT-FLAT 1m x5 16ch x6 88ch 16ch x6 16ch x6 32chx3 to trigger circuit LEMO BNC BNC - LEMO 変換 FLAT LEMO - BNC 変換
1. BxN(x!V) 2. RFxN(x!V) NIM Coin N-RY 011 Discri RF Delay トリガーロジック 回路図 NIM Coin N-TM 103 S.C. L Discri Delay Discri S.C. R Discri CAMAC Discri 3412 NIM Coin N-RS 413 V2 HIME L x88ch 1. Exp 2. Self 3. Tcal OR or OR P752 Delay NIM Coin N-TM 103 NIM Coin N-TM 103 Delay QDC V792 GATE GG F/F CAMAC Discri 3412 Multi-out Linear F/F START HIME R x88ch TDC V775 Discri Discri Delay Delay GG (Latch) TKY-0240A DAQ BUSY CLR F/F VETO L x3ch NIM OR P752 HIME self Discri OR P752 Delay VETO R x3ch Discri VETO self START Tcal RIS-0300 Delay TEST IN CAMAC Discri 3412 STOP
武内さん:200ns 小林さん:300ns