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Optimization of Carbon Nanotube Field-Effect Transistors (FETs). Alexandra Ford NSE 203/EE 235 Class Presentation March 5, 2007. Two Papers I Will Be Presenting Today:. How to Optimize a CNFET. Two papers discuss how to optimize a carbon nanotube FET to have
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Optimization of Carbon Nanotube Field-Effect Transistors (FETs) Alexandra Ford NSE 203/EE 235 Class Presentation March 5, 2007
How to Optimize a CNFET • Two papers discuss how to optimize a carbon nanotube FET to have • High ON current and conductance (max = 4e2/h) • High ON/OFF current ratios • Steep switching (max = 60 mV/decade at room T) • Highly scaled gate dielectrics and channels • Supression of ambipolar conduction by optimization of S/D contacts to carbon nanotubes(Pd contacts to electrostatically (1) or K (2) doped nanotube segments) and integration of high-quality thin gate insulator films (HfO2)
To Fabricate a P-Channel CNFET • Ohmic Pd-tube contact • 8 nm HfO2 gate dielectric • Al top-gate • Two tube segments outside the top-gate region are electrostatically “doped” by a back gate and act as S/D electrodes • Highest performance FET thus far (back gate constant bias VGS_BACK = -2V)
P-Channel CNFET Electrical Properties • Top-gate, for tube diameter d=2.3 nm, channel length L=2 mm: • Subthreshold swing of 80 mV/decade • Transconductance of gm=dIDS/dVDS|VDS=20 mS (~5000 S/m when normalized by tube diameter) • ON current of ION_sat=15-20 mA (~3750 mA/mm) • ON conductance of GON=0.1 x 4e2/h • gm and ION_satare higher than the state-of-the-art Si p-MOSFET by a factor of 5 at similar gate overdrive VDS = -0.3V -0.2V -0.1V
P-Channel CNFET Electrical Properties • Top-gate geometry (Pd-electrostatically “doped” nanotube segment contact or DopedSD-FET) has superior subthreshold swing compared to back-gate geometry (Pd-tube contact or MetalSD-FET) • 70-80 mV/decade vs 130 mV/decade • Likely due to more efficient electrostatic gating for the high-k/top-gate stack (top-gate capacitance is near the quantum capacitance for a SWNT=4pF/cm) • DopedSD-FET has supressedambipolar conduction compared to MetalSD-FET: VDS = -0.3V -0.2V -0.1V VDS = -0.3V -0.2V -0.1V DopedSD-FET MetalSD-FET
What Happens When You Chemically Dope the S/D Nanotube Segments? • Becomes possible to make a n-type CNFET – n-type CNFETs are more difficult to successfully fabricate because of high Schottky barrier contacts for high on-states • The chemical doping can suppress the Schottky barriers at the contacts, resulting in devices with subthreshold swings of 70 mV/decade, ON/OFF ratios of 106, and negligible ambipolar conduction • As-made devices (back-gate geometry, before doping) are p-type FETs; doping with K (heavy electron donation) increases ION and GON from 5 mA and 0.3 e2/h to 20 mA and e2/h, suggesting high metal-semiconductor contact transparency (TMS ~ 1)
Before and After K Doping – Top-gate • BLUE = p-FET (before doping) - • electrostatically p-doped contacts by applying • a back gate voltage of -15V • RED = n-FET (same device after moderate • doping with K) - • this creates an n+-i-n+ structure similar to a • conventional n-MOSFET (nanotube segments • outside the gate Ti/Pd metal/HfO2 stack are • exposed to K vapor doping to form the n+ • regions, are under gate remains intrinsic)
Before and After K Doping – Top-gate • These IDS-VGS and IDS-VDS plots show that the n-FET (K-doped) and p-FET (electrostatically doped) have near-symmetrical characteristics: • n-FET and p-FET both have on-currents ION of 8 mA (for VDS = 0.5 V) • n-FET and p-FET transconductance values of 20 and 10 mS, respectively • n-FET and p-FET have subthreshold swings of 70-80 mV/decade • AND note that ION/IOFF for the n-FET is ~106 and there is no significant ambipolar p-channel conduction
Comparison to Si n-MOSFET • Near-transparent n-type contacts can be formed by chemical doping with K, mainly as a result of Schottky barrier height reduction at the metal-tube junctions • Heavy and moderately doped n-FETs have higher on-currents at all ION/IOFF values than a 100 nm node Si n-MOSFET (gate length L=50 nm)
Conclusion • p-CNFETs and n-CNFETS can be obtained by using Pd contacts, high-dielectric-constant HfO2 films as gate insulators, and electrostatic (for p-FET) or chemical (for n-FET) doping