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J. Holma CERN TE/ABT, Geneva, Switzerland Acknowledgement M.J. Barnes CERN

Present Status of Inductive Adder Development for the CLIC DR Kicker Systems. J. Holma CERN TE/ABT, Geneva, Switzerland Acknowledgement M.J. Barnes CERN. Overview. Ideal current for 1 GHz option:. Background CLIC Layout with Damping Ring (DR) kickers

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J. Holma CERN TE/ABT, Geneva, Switzerland Acknowledgement M.J. Barnes CERN

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  1. Present Status of Inductive Adder Development for the CLIC DR Kicker Systems J. Holma CERN TE/ABT, Geneva, Switzerland Acknowledgement M.J. Barnes CERN CLIC WS, CERN, 2014

  2. Overview Ideal current for 1 GHz option: • Background • CLIC Layout with Damping Ring (DR) kickers • Specifications for CLIC DR Extraction Kicker System • Challenges and Issues • Inductive Adder Design • Schematic • Contributors to the Droop of the Output Waveform • Compensation of Droop and Ripple • Status of the Prototyping • Specifications for the First Prototype Inductive Adder • HV Measurements on the First Prototype Adder • Passive Droop Compensation at 1 kV • 1.2 kV Pulse with < ±0.2 % Droop and Ripple • Summary and Future Work CLIC WS, CERN, 2014

  3. CLIC General Layout Extraction Kicker Damping Ring (DR) Injection Kicker Damping ring kickers DR: Damping Ring; PDR: Pre-Damping Ring. • PDR & DR Kickers ( ): • One injection and extraction system per ring and per beam (8 systems); • Damping rings reduce beam emittance; hence kickers must be high stability (low ripple); • Low beam coupling impedance and good field homogeneity are required (talk by C. Belver-Aguilar). CLIC WS, CERN, 2014

  4. Specifications for the CLIC DR Extraction Kicker Systems Extraction Kicker Damping Ring (DR) Injection Kicker Damping ring kickers Drawing of the CLIC DR extractionkicker (Courtesy of C. Belver-Aguilar) Schematic of a kicker system • NOTE: • For rise/fall times, 100 ns desired! • Close to 0 V required between pulses! CLIC DR kicker pulse definition CLIC WS, CERN, 2014

  5. Challenges and Issues Extraction Kicker Damping Ring (DR) Injection Kicker Schematic of a kicker system • ±0.02 % (± 2.5 V)requirement for the flat-top stability of±12.5 kV, 160 to ~900 ns • pulse is an extremely demanding specification! • An order of magnitude betterthan in any existing kicker systems! • Compensation of droop and ripple of the output voltage is required. • Adequate impedance matching to minimize duration of settling time: • Impedance (and field homogeneity) of the stripline kicker has been optimized: unfortunately the impedance cannot be 50 Ω for both power-off (even) and power-on (odd) operation modes! • Odd-mode impedance of the striplines is ~41 Ω (see talk by C. Belver-Aguilar), which causes settling time to be ~100 ns. Therefore the pulse flat-top length is at least ~260 ns (2 GHz option) • Suitable high precision measurements of the pulse in the laboratory: • better precision than ±2.5 V in 12.5 kV required! CLIC DR kicker pulse definition CLIC WS, CERN, 2014

  6. Inductive Adder • Many primary “layers”, each with solid-state switches • The output voltage is the sum of the voltages of the primary constant voltage layers • +Control electronics referenced to ground • +No electronics referenced to high voltage despite the high voltage output of the adder • + The output voltage can be modulated during the pulse with an analogue modulation layer • +Modularity: the same design can potentially be used for kickers with different specifications (CLIC PDR & DR kicker modulators) • +Redundancy and machine safety: if one switch or layer fails, the adder still gives full voltage or a significant portion of the required output pulse • +Possibility to generate positive or negative output pulses with the same adder: the polarity of the pulse can be changed by grounding the other end of the output of the adder Schematic of an inductiveadder A prototype inductive adder CLIC WS, CERN, 2014

  7. Contributors to the Droop of the Output Waveform of an Inductive Adder • The droop of the output pulse of an inductive adder is caused by: • The voltage droop of the storage capacitor (Cs) as it [slightly] supplies charge during the pulse • The resistive losses in the primary switch and in the primary circuit (Rsw) • Only the voltage droop of the capacitors can be compensated by adding more capacitance per layer! • The only methods to effectively decrease the droop, caused by a combination of resistive losses and magnetizing inductance of the transformer core, is to apply either passive or active analogue modulation (or both) for the output pulse. • These methods are necessary to reach very low droop (<< 1 %). Vlayer Vcap Lm Switch Capacitor voltage Vcap and voltage of a layer Vlayer during a pulse. Cs = 24 uF, Rsw = 0.34 Ω and Rload/N = 10 Ω. Simplified schematic of a constant voltage layer of an inductive adder Simplified model of a layer of an inductive adder during the pulse CLIC WS, CERN, 2014

  8. Compensation of Droop and Ripple No capacitor here • In analogue modulation layer, there is no storage capacitor but there is resistor Ra • Resistor Ra is effectively in series with the load • Load voltage: • VMax is the sum of the voltages over the layers except the analogue modulation layer: VLoad ≤ VMax! • Resistor Ra is in parallel with magnetizing inductance Lm • Compensation modes: • PASSIVE MODE: During the pulse, current through Lm increases, which causes current through Ra to decrease. Therefore, voltageover Radecreases, whichcausesVLoad to increase. Thisvoltagechange is reverse in comparisonwithvoltagedroopcausedbystoragecapacictors in otherlayers. • ACTIVE MODE: Alinear RF power transistor provides a shunt path for the current through resistor Ra. Therefore, the voltage over Ra can be controlled by controlling the current through the RF power transistor. RF Power Transistor Ra Lm VMax VMax VLoad VRa CLIC WS, CERN, 2014

  9. Compensation of Droop and Ripple Droop < 0.1 % Droop ~ 0.5 % ±0.02 % Droop > 1.5 % Simulated droop compensation with passive analogue modulation Simulated droop and ripple compensation with active analogue modulation • Passive analogue modulation – partial droop compensation • Active analogue modulation – partial droop and ripple compensation • For the CLIC DR kicker modulator, both PASSIVE and ACTIVE modulation methods will be applied! CLIC WS, CERN, 2014

  10. The Prototype Inductive Adder • The purpose of the prototype inductive adder is: • To verify experimentally design steps for the high precision inductive adder • To test both passive and active analogue modulation • To approach the required ±0.02 % flat-top stability for the output pulse, as specified for the CLIC DR extraction kicker modulator The prototype inductive adder with two half-layers inserted * limited by transformer cores, design value 900 ns CLIC WS, CERN, 2014

  11. Measurements on the Prototype Inductive Adder Prototype inductive adder Signal generators Trigger inputs Oscilloscope DC power supplies The prototype inductive adder with the measurement setup CLIC WS, CERN, 2014

  12. Measurements on the Prototype Inductive Adder In initial measurements, only one branch per half-layer PCB was powered! 2 branches per layer. The prototype inductive adder with a current transformer and a load CLIC WS, CERN, 2014

  13. Measurements: Output up to 1.4 kV – No Modulation • Setup for the measurement: • The prototype adder with 5 layers • 1 branch powered per half-layer PCB, 2 branches per layer • Capacitors (24 µF/layer) charged initially to 302 V • 50 Ω, 18 kV load by Diconex • No modulation applied. • Output pulse parameters • Output voltage: 1.4 kV • Droop: ~1.5 % for 300 ns flat-top (~0.8 % for 160 ns) • Ripple: ±0.36 % (maximum) • Small backswing (~4 V). • Comparison with simulations • Simulated waveform from a PSpice model, based on the design of the prototype inductive adder • The measured droop is very close to the predicted value (~1.5 %). • Conclusion: • The overall electrical design of the prototype inductive adder is correct. Vload1.4 kV Flat-top~300 ns ±0.2 % 160 ns CLIC WS, CERN, 2014

  14. Measurements: Droop Compensation with 1 kV • Setup for the measurement: • The prototype adder with 4 constant voltage layers and a passive analogue modulation layer • 1 branch powered per half-layer PCB, 2 branches per layer • Capacitors (24 µF/layer) charged initially to 270 V (w/o modulation) or 285 V (with modulation). • Output pulse parameters • Without modulation: • Vload= 1.023 kV, ΔUload = 15 V (1.5 %). • With modulation: • Vload = 1.002 kV, ΔUload = 10 V (1.0 %). • The passive analogue modulation layer effectively reduced the droop with 1 kV output voltage from 1.5 % (w/o modulation) to 1.0 % (with modulation). • Comparison with the CLIC DR kicker parameters • 1.0 % of droop in 350 ns corresponds to 0.46 % (±0.23 %) in 160 ns (flat-top length for CLIC DR extraction kicker) • The droop can be decreased further by optimizing the passive analogue modulation layer, adding more capacitance and switches on the layers, and applying active analogue modulation. Flat-top~350 ns 350 ns 10 V 15 V Connection of Ra on the passive analogue modulation layer. CLIC WS, CERN, 2014

  15. Measurements: 1.2 kV pulse with < ±0.2 % droop and ripple Vload1.2 kV 160 ns 160 ns Zoom of 160 ns flat-top Vripple+droop3.8 V, ±0.16 % • Setup for the measurement: • 4constant voltage layers and a passive analogue modulation layer • 1 branch powered per half-layer PCB, 2 branches per layer • Capacitors (24 µF/layer) initially charged to 350 V (Ra = 7.9 Ω) • Notes: • Tektronix scope used (DPO 5034) has a nominal vertical resolution of 8 bits (< ±0.4%) – can be improved with averaging • Picoscope 4227 (100 MHz, 2 Channel, 12-bit USB Oscilloscope) purchased and to be tested in the near future. CLIC WS, CERN, 2014

  16. Measurements: 2.5 kV Output Pulse Vload2.5 kV 80 ns 260 ns 100 ns 80 ns • Setup for the measurement: • The prototype adder with 4 constant voltage layers and a passive analogue modulation layer • 1 branch powered per half-layer PCB, 2 branches per layer • Capacitors (24 µF/layer) charged initially to 700 V (Ra = 4.0 Ω, droop ±1.5 %) CLIC WS, CERN, 2014

  17. Summary • The first 5-layer prototype inductive adder is currently being tested at CERN • The initial high voltage measurements have verified that the prototype adder performs as expected • The final goal is to reach the stability requirement for the CLIC DR extraction kicker modulator • Another 5-layer inductive adder will be assembled in February 2014. • The prototype adders will be used to test both passive and active analogue modulation methods • Two prototype adders allow bipolar output pulses and measurements of pulses with oppostive polarity with a single current transformer: the sensitivity of the measurements of the pulse flat-top can be improved. • The design of the full-scale 12.5 kV, 250 A, CLIC DR kicker prototype inductive adder will be based on the design of the two 5-layer prototype inductive adders. CLIC WS, CERN, 2014

  18. Questions & Comments? CLIC WS, CERN, 2014

  19. References and Bibliography • Holma J., Barnes M.J.: ”Initial Measurements on a Prototype Inductive Adder for the CLIC Kicker Systems”, Proc. of PPC’13, San Francisco, CA, USA, June 16-21, 2013. • Holma J., Barnes M.J., Ovaska S.J.: ”Modelling of Parasitic Inductances of a High Precision Inductive Adder for CLIC”, Proc. of IPAC’13, Shanghai, China, May 12-17, 2013. • Holma J., Barnes M.J.: “Sensitivity Analysis for the CLIC Damping Ring Inductive Adder”, Proc. of Int. Power Modulators and High Voltage Conference, San Diego, CA, USA, Jun. 3-7, 2012. • Holma J., Barnes M.J.:“Evaluation of Components for the High Precision Inductive Adder for the CLIC Damping Rings”, Proc. of IPAC 2012, New Orleans, USA, May 20-26, 2012. • Holma J., Barnes M.J.: “Pulse Power Modulator Development for the CLIC Damping Ring Kickers”, CLIC-Note-938, CERN, Geneva, Switzerland, April 27, 2012. • Holma J., “Present Status of Development of DR Extraction Kicker System”, International Workshop on Future Linear Colliders, Granada, Spain, 26-30 Sept., 2011. • Holma J., Barnes M.J.: “Preliminary design of an inductive adder for CLIC damping rings”, Proc. of IPAC 2011, San Sebastián, Spain, 4-9 Sept., 2011. • Holma J., Barnes M.J., Ovaska S.: “Preliminary design of the pulse generator for the CLIC damping ring extraction system”, Proc. of 18th IEEE International Pulsed Power Conference, Chicago, Illinois, USA, 19-23 Jun, 2011. CLIC WS, CERN, 2014

  20. Spare Slides CLIC WS, CERN, 2014

  21. Ideas for High Precision Measurements of the Output Pulses • ±0.02 % requirement for the flat-top stability of±12.5 kV, 160 to ~900 ns pulse for DR extraction kicker is an extremely demanding specification : • An order of magnitude betterthan in any existing systems! • Active compensation of droop and ripple will be studied further with the prototype • Adequate impedance matching to minimize duration of settling time • Suitable high precision measurements of the pulse in the laboratory • Droop and ripple measurement: Pulse from an inductive adder and output of a high precision DC source with an opposite polarity are summed to compare pulse with an ”ideal” flat-top • Reproducibility and stability: Pulses from two inductive adders are fed through a single current transformer with opposite sense, which ideally sums to zero field if the pulses are identical • The kicker system will finally be tested in an accelerator facility • Se Schematic of kicker system with an inductive adder CLIC WS, CERN, 2014

  22. Measurements on the First Prototype Inductive Adder (cont’d) • Polarity change of the load voltage by grouding other end of the stack • The polarity of the pulse capacitors remain the same; the only difference is that the positions of the load connector and short-circuit are swapped • For a stripline kicker, positive and negative pulses are needed simultaneously, therefore two identical inductive adders will be built. VTrigger VLoad VLoad VSwitch(D-S) VSwitch(D-S) VTrigger Output = TOP of the stack Negative load voltage Output = BOTTOM of the stack Positive load voltage CLIC WS, CERN, 2014

  23. 3D-Modelling of the Inductive Adder • The output impedance of the inductive adder has to be very well matched to the kicker magnet and the load, in order to generate the required flat-top pulses with minimum rise and fall times. • New methodology has been developed to estimate the parasitic circuit elements of the inductive adder structure in order to design the adder to have the desired electrical behaviour: • FastHenry code has been used to predict the primary leakage inductance of the inductive adder. The simulations have been verified by measurements of the prototype inductive adder. • These studies are valuable for gaining experience in designing pulse modulators with very high performance and allows to finish the design without several iteration steps. Cross-section of a single branch The FastHenry model of a single branch A single branch under impedance measurement CLIC WS, CERN, 2014

  24. Future Work re Inductive Adders • Dump kicker modulator for CLIC damping rings • The CLIC DR extraction kicker inductive adder (12.5 kV; 20 layers) would have 8-10 extra layers which can be switched on to abort the beam (17.5 kV pulse) • Pulse generator (~12 kV, 1 kHz) for breakdown tests of CLIC RF cavities • Combiner ring extraction kicker modulator for CLIC • Specifications (CR 1): 10 kV [50 Ω], pulse duration up to 450 ns, burst-rate up to 688 kHz for 140 µs (average repetition rate ~5 kHz) • An active (fast) reset circuit may be a solution to keep the transformer core sizes reasonable Schematic of DR extraction kicker inductive adder with extra layers for dump kicker CLIC WS, CERN, 2014

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