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An Introduction to VHDL Using Altera’s Quartus II IDE. Dr. William M. Jones Coastal Carolina University Numbers and Bytes Meeting 20 OCT 2008. Pre-Intro. VHDL Very Hard Difficult Language Jk VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuits Intended uses
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An Introduction to VHDL Using Altera’s Quartus II IDE Dr. William M. Jones Coastal Carolina University Numbers and Bytes Meeting 20 OCT 2008
Pre-Intro • VHDL • Very Hard Difficult Language • Jk • VHSIC Hardware Description Language • VHSIC • Very High Speed Integrated Circuits • Intended uses • Circuit simulation • Circuit synthesis (realization) • FPGA’s, (C)PLDs, ASICs VHDL Quick Start
Some Background • VHDL vice Verilog • Altera and Xilinx • VHDL is a language • But, is very different from traditional languages • In general, all statements are CONCURRENT (parallel) • Traditional is SEQUENTIAL • Typically referred to as code as opposed to a program • VHDL is not case sensitive • PROCESS, FUNCTION, PROCEDURE • Only places were sequential behavior is seen VHDL Quick Start
Basic VHDL Code Parts • LIBRARY • Like #include <stdio.h> in C or import in JAVA • Commonly used pieces of code • 2 are generally included by default • ENTITY • List of specifications for input and output PORTS • Kinda like function prototypes in C (provides interface) • ARCHITECTURE • Provides a description of how the circuit should behave VHDL Quick Start
LIBRARY LIBRARY library_name; USE library_name.package_name.package_parts; LIBRARY ieee; USE ieee.std_logic_1164.all; LIBRARY std; -- included by default USE std.standard.all; LIBRARY work; -- included by default USE work.all; VHDL Quick Start
ENTITY (Modeling Interfaces) (VHDL-93) • Entity declaration • describes the input/output ports of a module entity name port names port mode (direction) entity reg4 isport ( d0, d1, d2, d3, en, clk : in bit; q0, q1, q2, q3 : out bit );end entity reg4; punctuation reserved words port type VHDL Quick Start
PORTS – Signal Modes • IN • Unidirectional • OUT • Unidirectional • INOUT • Bidirectional • BUFFER • Used when output signal needs to be used internally VHDL Quick Start
Putting Them Together VHDL Quick Start
A Simple Multiplexer VHDL Quick Start
MUX Implementation with Pure Logic VHDL Quick Start
Synthesized Hardware (Pure Logic) But what do you do now? VHDL Quick Start
Altera DE 2 Board VHDL Quick Start
MUX Implementation with WHEN/ELSE VHDL Quick Start
Synthesized Hardware (WHEN/ELSE) VHDL Quick Start
A Simple ALU VHDL Quick Start
ALU Specifications VHDL Quick Start
ALU Part 1 VHDL Quick Start
ALU Part 2 VHDL Quick Start
ALU Part 3 VHDL Quick Start
Kickin’ It Up A Notch Combinational v. Sequential LOGIC VHDL Quick Start
Concurrent v. Sequential Code • Code placed inside a PROCESS, FUNCTION, or PROCEDURE is executed sequentially • Otherwise the does is executed concurrently • In parallel • Order of statements would not matter • Often called ‘dataflow’ code • With only a few exceptions purely concurrent code will only produce ‘combinational’ circuits • Sequential code must be employed to produce sequential logic circuits (this code can produce both in fact) VHDL Quick Start
A Simple Counter (Sequential Code Intro) VHDL Quick Start
Simple Counter Code VHDL Quick Start
Synthesized Hardware (Counter) VHDL Quick Start
Counter (Zoom 1) VHDL Quick Start
Counter (Zoom 2) VHDL Quick Start
A Counter With A Display VHDL Quick Start
Counter With Display VHDL (Part 1) VHDL Quick Start
Counter With Display (Part 2) VHDL Quick Start
Counter With Display (Part 3) VHDL Quick Start
Counter With Display (Part 4) VHDL Quick Start
Synthesized HW (Partial) VHDL Quick Start
Creating A Symbol File (Schematic) VHDL Quick Start
End of N&B Presentation Have a nice day!