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Development of 3D Detectors at ITC-irst: Fabrication and Simulation Results

This article discusses the development of 3D detectors at ITC-irst, including the fabrication process, technological tests, and preliminary electrical results. The study utilizes TCAD simulations to analyze the static and dynamic behavior of the detectors.

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Development of 3D Detectors at ITC-irst: Fabrication and Simulation Results

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  1. Development of 3D detectors at ITC-irst Maurizio Boscardina, Claudio Piemontea, Alberto Pozzaa, Sabina Ronchina, Nicola Zorzia, Gian-Franco Dalla Bettab a ITC-irst, Microsystems Division, via Sommarive, 18 38050 Povo di Trento, Italy b DIT, University of Trento, Via Sommarive, 14, 38050 Povo di Trento, Italy SCIPP

  2. Outline • Introduction • Single-Type Column 3D detectors • Simulation results • Technological tests • Fabrication of the first batch • Preliminary electrical results • Conclusion SCIPP

  3. Introduction • ITC-irst is developing the process for the fabrication • of 3D sensors. • Framework: • RD50 collaboration - for the development of radiation • tolerant detectors • INFN-PAT agreement • We have started with a simplified process, since all • necessary clean-room equipment is not available yet SCIPP

  4. “Standard” 3D detectors - concept First 3D architecture, proposed by S.I. Parker et al. [1] in 1997: columnar electrodes of both doping types ionizing particle p-columns n-columns wafer surface • Short distance between electrodes: • low full depletion voltage • short collection distance • more radiation tolerant • than planar detectors!! n-type substrate DRAWBACK: Fabrication process rather long and not standard, so mass production of 3D devices very critical and very expensive. [1] S.I. Parker et al., Nucl. Instr. Meth. Phys. Res. A 395 (1997) 328 SCIPP

  5. resist n+ polysilicon 3) hole doping and filling 2) n+ hole definition and etching metal resist p+ polysilicon 6) Metal deposition and definition 4) p+ hole definition and etching 5) hole doping and filling “Standard” 3D detectors - fabrication Kenney et al. IEEE TNS, vol. 46, n. 4 (1999) detector wafer oxide support wafer 1) wafer bonding SCIPP

  6. ionizing particle cross-section between two electrodes n+ n+ holes drift in the central region and diffuse towards p+ contact electrons are swept away by the transversal field Single-Type-Column 3D detectors - concept Sketch of the detector: Functioning: n-columns p-type substrate grid-like bulk contact Etching and column doping performed only once SCIPP

  7. n+ electrodes p-type substrate Uniform p+ layer 3DSTC detectors - concept (2) Further simplification: not passing-through holes No need of support wafer. Bulk contact is provided by a Backside uniform p+ implant single side process. SCIPP

  8. TCAD Simulations - static (1) 3D simulations are necessary DEVICE3D tool by Silvaco 50mm cell n+ • p-type substrate • Wafer thickness: 300mm • Holes: 5mm-radius • 250mm-deep Important to exploit the structure symmetries to minimize the region to be simulated SCIPP

  9. 50mm 0V -5V 300mm -10V TCAD Simulations - static (2) Potential distribution (horizontal cross-section) Potential distribution (vertical cross-section) null field regions -15V SCIPP

  10. TCAD Simulations - static (3) Potential and Electric field along a cut-line from the electrode to the center of the cell Na=1e131/cm3 Na=1e121/cm3 Na=5e121/cm3 Na=5e121/cm3 Na=1e121/cm3 Na=1e131/cm3 To increase the electric field strength one can act on the substrate doping concentration SCIPP

  11. TCAD Simulations - dynamic (1) Current signal in response to an ionizing particle. Vertical tracks in 3 different positions Electron cloud evolution (b) a c b n+ n+ 1 2 n+ n+ 3 4 SCIPP

  12. TCAD Simulations - dynamic (2) Case c. Nsub=1e13 cm-3 In the worst case the induced current peak is within 10ns Nsub=5e12 cm-3 Current (A) Nsub=1e12 cm-3 10ns Case b. Nsub=1e13 cm-3 For a hit 5mm from the electrode the peak is within 1ns. Nsub=5e12 cm-3 Current (A) Nsub=1e12 cm-3 1ns SCIPP

  13. TCAD Simulations – critical points evidenced • High electric field at the bottom of the hole. • Anyway we should not reach critical values because of the • low bias voltages needed. • In case of p-spray isolation, high electric field at the • column/p-spray junction. • Again, may be of concern depending on the bias • voltage needed. • Long low tail in the current signal due to hole diffusion. • Simulation have shown that this effect can be strongly • minimized using passing-through electrodes. SCIPP

  14. Technological tests - lithography as-deposited: Photoresist tends to penetrate inside the hole forming a thicker layer in these region after exposure and development: residual photoresist in the hole region Important to note that resist can be defined in the proximity of the hole. The resist trapped in the hole is removed after the process SCIPP

  15. Technological tests - deposition Poly and oxide deposition top oxide surface hole poly bottom oxide hole poly SCIPP

  16. Technological tests – oxide growth Oxide Growth (500nm) in a 5mm diameter hole top bottom oxide metal hole oxide SCIPP

  17. Technological tests – metal sputtering Aluminum does not penetrate inside the hole contacts have to be made on the wafer surface aluminum hole SCIPP

  18. Fabrication process (1) • initial oxide • p+-doping of back • Isolation: p-stop or p-spray • masking for deep- RIE process • deep-RIE (CNM,Barcelona-Spain) p-stop oxide p+ doping holes SCIPP

  19. Fabrication process (2) • P-diffusion (no hole filling) • Oxidation (hole passivation) • Opening contacts • Metal and sintering P- diffused regions metal contacts Hole passivation SCIPP

  20. Mask layout “Large” strip-like detectors Small version of strip detectors Planar and 3D test structures “Low density layout” to increase mechanical robustness of the wafer SCIPP

  21. Mask Layout-Test structures Standard (planar) test structures 10x10 matrix 3D-Diode Ø hole 10 µm 44 holes GR Pitch 80 µm SCIPP

  22. Mask layout - strip detectors Inner guard ring (bias line) metal p-stop hole • AC and DC coupling • Inter-columns pitch 80-100 m • Two different p-stop layouts • Holes Ø 6 or 10 m Contact opening n+ SCIPP

  23. Fabrication run: main characteristics • Substrate: Si High Resistivity,p-type, <100> • FZ (500 m) >5.0 kcm • Cz (300m) >1.8 kcm Wafers with lower resistivity are not easy to find • Surface isolation: • p-stop • p-spray SCIPP

  24. SEM micrographs Top-side of a column metal oxide 6 m Portion of a strip detector strip 100 m Column-section SCIPP

  25. Electrical Characterization (1) Standard (planar) test structures Different sub-types and thicknesses 2% to 13% variation on single wafer Ileak measured below full depletion due to breakdown electrical parameters compatible with standard planar processes DRIE does not endanger device performances SCIPP

  26. diode • guard ring • diode • guard ring Electrical Characterization (2)IV measurements 10x10 matrix Ø hole 10 µm Pitch 80 µm Active area ~0.64 mm2 3D-Diode Ileak/column @ 20V 0.33 ±0.24 pA Ileak/column @ 20V 0.67 ±0.12 pA FZ CZ P-stop P-spray P-stop P-spray SCIPP

  27. 30 25 20 15 Detectors count 10 5 0 0 5 10 15 20 25 30 35 40 45 50 >50 I bias line [nA] Electrical Characterization (3) Strip detectors Current distribution @ 40V of 70 different devices 1detector: 230 columns x 64 strips on 1 cm2 ~ 15000 columns FZ average current per column < 1pA Good process yield SCIPP

  28. Conclusions A new type of 3D detector has been conceived which leads to a significant simplification of the process: • hole etching performed only once • no hole filling • no wafer bonding First production is completed: • Good electrical parameters (DRIE does not endanger device performance) • Low leakage currents< 1pA/column and BD ~ 50Vfor p-spray and >100Vfor p-stop in 3Ddiodes • Good yield for strip detectors(Current/hole< 1pA/columnfor93%of detectors) Accurate analysis of CV measurement results is in progress with the aid of TCAD simulations … SCIPP

  29. Lateral depletion-voltage Preliminary “3d-diode”/GR capacitance measurements Weak capacitive coupling at very low voltages (conductive substrate layer between columns) Capacitive coupling between 40 columns (100um=pitch, 150um depth) Vback Cint-Vback ~ 5V lateral full depletion voltage (100µm pitch) Cint

  30. Backplane full-depletion-voltage Preliminary “3d-diode”/back capacitance measurements C-V Lateral depletion contribution to measured capacitance at low voltages Linear 1/C2 vs V region corresponding to the same doping level of planar diodes Saturation capacitance corresponding to a depleted width of ~ 150µm)  Column depth ~ 150µm 1/C2-V ~ 40V full depletion voltage (300µm wafer)

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