Statistical Critical Path Selection for Timing Validation

1. Statistical Critical Path Selection for Timing Validation Kai Yang, Kwang-Ting Cheng, and Li-C Wang Department of Electrical and Computer Engineering University of California, Santa Barbara

2. Outline • Abstract • Background • Motivation • Universal Representative Path Set • Statistical Timing Simulator • UR-Path Construction • Experimental Result • Conclusion and Future Works

3. Outline • Abstract • Background • Motivation • Universal Representative Path Set • Statistical Timing Simulator • UR-Path Construction • Experimental Result • Conclusion and Future Works

4. Abstract Statistical critical path selection for timing validation • Path selection aims at tolerating inaccurate timing models • Develop an efficient statistical timing simulator which can model both intra-die and inter-die process variation • Analyze the timing validation quality using the generated patterns for the selected paths • Previous researches utilize static path analysis

5. Outline • Abstract • Background • Motivation • Universal Representative Path Set • Statistical Timing Simulator • UR-Path Construction • Experimental Result • Conclusion and Future Works

6. Background • Continuous shrinking of device feature size increases the following timing effects: • Process Variation • Power Noise • Crosstalk • Random Defects • Thermal Effects • Modeling Issue • Traditional discrete-value timing models are no longer effective • Statistical timing modeling make more sense in deep sub-micron domain

7. Background – Timing Validation A B C • Verify the design with the timing constraints • Functional pattern v.s. structure-based pattern • Focus on the impact of process variations • No target on spot defects • Structure-based pattern • Critical path selection for timing validation • Test pattern generation for selected path set

8. Outline • Abstract • Background • Motivation • Universal Representative Path Set • Statistical Timing Simulator • UR-Path Construction • Experimental Result • Conclusion and Future Works

9. Motivation • Traditional discrete-value modeling not able to efficiently capture deep sub-micron timing effects • Even with a statistical methodology, an accurate timing model may not be available during the design phase • Even with an accurate timing model, the number of selected critical paths for timing validation may be huge

10. Outline • Abstract • Background • Motivation • Universal Representative Path Set • Statistical Timing Simulator • UR-Path Construction • Experimental Result • Conclusion and Future Works

11. Universal-Representative Path • Definition: Universal-Representative Path Set (UR) • If we make sure the delays of these paths are less than a • given clock period, then we can guarantee that the worst- • case circuit timing is also less than the clock period.

12. Factor Analysis v.s. UR-Path Statistical Timing Simulation Statistical Timing Simulation  regression ATPG ATPG Representative paths reduced to 3 factors regression Path Selection 6 aspects in your questionnaire Identify the underlying structure of data matrix Y=function of (3 factors)  Y’=function of (6 variables) Factor Analysis

13. Outline • Abstract • Background • Motivation • Universal Representative Path Set • Statistical Timing Simulator • UR-Path Construction • Experimental Result • Conclusion and Future Works

14. Statistical Timing Simulator - DSIM • Objective: build a flexible, accurate, and efficient timing simulator • Support flexible interface for incorporating different DSM timing effects • Inter-Die Process Variation • Hierarchical Intra-Die Process Variation Modeling • Allow us to study the impact of process variations • software released ! • Download source code at http://cadlab.ece.ucsb.edu

15. Statistical Timing Simulator Statistical Delay Library Layout Information Intra-Die Process Variation Profile Delay Random Variables Statistical Timing Simulator -- DSIM Simulation Patterns Circuit Netlist Sample 1 Sample 2 Sample K ….. Delay 1 Delay 2 Delay K

16. Experimental Result and Efficiency Statistical Simulation Efficiency – 100 samples and 1000 random patterns – P4 2GHz Linux workstation

17. Intra-Die Process Variations • Process variation can be divided into two categories • Inter-Die Variation • Intra-Die Variation • Inter-die variation is more likely to be random • Modeled in the statistical delay library • Intra-die variation is spatially correlated which is hard to directly modeled into the delay library • Proximately-close devices may have similar behaviors

18. Hierarchical Intra-Die Process Variation Modeling • Originally developed by David Blaauw’s group on channel-length modeling • Each region is associated with a variation parameter Cn • Cn characterize the change in standard deviation C10 Example C20 Proximity-closer devices have a stronger correlations in theirs delay C30 Layout

19. Impact of Modeled Intra-Die Process Variation • Layout Information – UCLA Capo • Without real process variation profile, randomly setup Cn • For each region, the change of accumulative std in percentage is less or equal to 15% • 3000 critical path delay test patterns with 6 different variation profiles

20. Summary of DSIM clk • Each circuit sample has a different but fixed delay configuration • Given a set of patterns, the simulator performs timing simulation on each circuit sample • For a given clock and for each pattern, the simulator can compute the probability of circuit delay exceeding the clock • Consider the effect of intra-die process variations into timing simulation process Primary Output

21. Outline • Abstract • Background • Motivation • Universal Representative Path Set • Statistical Timing Simulator • UR-Path Construction • Experimental Result • Conclusion and Future Works

22. UR-Path Construction • Two-Phase algorithm • Path selection: • Select the superset of path (U-Path) from the whole path space which may affect the critical timing • Timing guard-band based selection method to tolerate inaccurate timing model • Path refinement: • Select the subset of path (UR-Path) from U-Path which can represent the timing behavior of the whole U-Path set

23. Phase-1: Path Selection Δ A B C clk 333 clk- Δ 319 • Goal:timing guard-band based method to select the set of path which may affect the critical timing • Construction of U-Path [iccad2002] • Given a clock clk and the threshold value Δ, U-Path includes all paths with non-zero critical probabilities to exceed the specified value clk- Δ. • For a large Δ will produce a large number of paths which will make the path selection very inefficient.  Path Refinement c5315 c5315

24. Phase-2: Path Refinement circuit sample Identify the path p has the largest critical probability circuit sample DSIM Remove those samples which p is longer than clk circuit sample For the remaining circuit samples, select the path with the largest critical probability, estimated based on all remaining samples circuit sample • Goal:Select a small set of path which can represent the timing behavior of U-Path • Timing behavior: the possibility to be longer than the clk Sample-based method [iccad2002]

25. Phase-2: Path Refinement Remaining paths sorted with mean delay UR-path set Pick one path p’ can calculate the correlation coefficient with each path in UR-set After phase-1, we get a set of UR-path but due to the inaccurate timing model, we need to enlarge the path set • Correlation based heuristic – statistical factor analysis • Select the paths which are more independent • Paths with high correlation tend to have similar timing behavior If the correlation is less than the given threshold value, include p’ into UR-path set

26. Outline • Abstract • Background • Motivation • Universal Representative Path Set • Statistical Timing Simulator • UR-Path Construction • Experimental Result • Conclusion and Future Works

27. Experimental Setup • Incorporate the statistical simulator to calculate the failing sample rate as the evaluation metric • Perform the proposed path selection with inter-die process variation only • Modeled directly in the statistical delay library • Evaluate the quality of the resulting pattern of the circuit samples with both intra-die and inter-die process variations • To demonstrate the proposed method can tolerate the inaccurate timing model

28. Metric: Failing Sample Rate Detected Failing Sample Rate = Detected Not-Detected + Statistical Timing Simulator Circuit Instance with both Inter-die and Intra-die variations Test set T Cause delay Exceeding clock? yes no Not-Detected Detected

29. Experimental Result • Construct UR-Path set with different correlation coefficient • Compare with other path selection strategies • The number of selected critical path converge quickly compare to the traditional selection methodology Ind32opt

30. Experimental Results c2670opt

31. Outline • Abstract • Background • Motivation • Universal Representative Path Set • Statistical Timing Simulator • UR-Path Construction • Experimental Result • Conclusion and Future Works

32. Conclusions and Future Work Conclusion • Propose a sample-based strategy to select statistical critical paths for timing validation. Experiment shows that the number of selected path converge quickly. • For some circuits, the proposed sampled-based method is much more efficiency than the traditional critical path selection. • Develop an efficient statistical timing simulator which can simulate both intra-die and inter-die delay. Future Work • Theoretically analyze the path selection problem for timing validation • Incorporate real process variation profiles to evaluate the proposed methodology