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Computer Architecture Principles Dr. Mike Frank

Computer Architecture Principles Dr. Mike Frank. CDA 5155 Summer 2003 Topics for Final Exam. Final Exam Format. This Friday, Aug. 8, in class, 1 ¼ hour (2:00-3:15 pm), six questions, some extra credit. Open book, open notes (like midterm)

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Computer Architecture Principles Dr. Mike Frank

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  1. Computer Architecture PrinciplesDr. Mike Frank CDA 5155Summer 2003 Topics for Final Exam

  2. Final Exam Format • This Friday, Aug. 8, in class, 1¼ hour (2:00-3:15 pm), six questions, some extra credit. • Open book, open notes (like midterm) • Writing a crib sheet is good way to review, & saves time flipping through book • You must bring (& use) a scientific calculator! • Coverage: • Comprehensive, but w. emphasis on new material. • ~40% will be on old material (from midterm) • Chapters 1-3 + Appendix A • ~60% will be on new material (since midterm) • Chapters 4-8 • Last year’s exams + some solutions are available; be sure to study + practice them!

  3. Final Exam Preparation Advice • Follow same guidelines as per midterm. • Practice the sample exam questions: • Last year’s sample midterm, midterm, sample final, final, make-up final. • Practice textbook exercises, even ones that were not assigned. • Exam questions may be similar. • Make a crib sheet with handy reference information. • So you don’t have to search through the book during the exam.

  4. Key Topics from Chapter 1 • Technology trends, Moore’s Law. (1.2-1.4) • IC cost and yield. (1.4) • Performance metrics & comparisons. (1.5) • Amdahl’s law & generalizations. (1.6) • CPU Performance Equation (1.6)

  5. Key Topics from Chapter 2 • ISA classifications (load-store, etc.). (2.2) • Memory addressing, addressing modes. (2.3) • Control flow instruction types. (2.9) • Instruction set encodings: Concepts.(2.5, 2.10) • MIPS ISA: Format, operations (2.12) • Load/stores, ALU ops, control instrs, FP ops.

  6. Key Topics from Appendix A • Simple RISC instruction execution cycle (A.1) • RTL descriptions of stages (A.3) • Simple RISC pipeline (A.3) • Hazards: Structural, data, control (A.2) • Stalls & impact on performance (A.2) • Bypassing & forwarding (A.2) • RAW/WAW/WAR hazards (A.4) • Hazard detection mechanisms (A.3) • Delayed branches, flushing, predict-(taken/not) (A.2)

  7. Key Appendix A Topics, cont. • Exceptions: Types, restart difficulties. (A.4) • Multi-cycle operations, parallel execution paths (A.5) • Latency & initiation interval (A.5) • MIPS pipeline example (A.6) • Dynamic scheduling w. scoreboarding (A.8)

  8. Key Chapter 3 Topics • Types of dependences: data/name/control (3.1) • Relation to hazards (3.1) • Dynamic scheduling w. Tomasulo’s alg. (3.2-3.3) • Dynamic branch prediction (3.4-3.5) • BPBs, correlating predictors (3.4) • Branch target buffers (3.5) • Multiple issue (3.6): Superscalar • Statically scheduled superscalar (3.6) • Dynamically scheduled superscalar, timing (3.7) • Hardware-based speculation w. reorder buffers (3.7) • Skip rest of ch. 3, from 3.8 onwards.

  9. Key Chapter 4 topics • Static scheduling (4.1) • Loop unrolling (4.1) • Static multiple-issue loop unrolling (4.1) • Static branch prediction (4.2) • Static scheduling for VLIW (4.3) • Software pipelining (4.3) • Conditional/predicated instructions (4.5) • Skip rest of ch. 4.

  10. Key Chapter 5 topics Memory Hierarchy • Intro, cache basics (5.1-5.2) • Placement, identification, replacement, wr strategy • Direct-mapped, set-associative, fully-associative • Random vs. LRU replacement • Write-thru vs. write-back, • write-allocate vs. write-around • Cache performance metrics (5.3) • Reducing cache misses (5.5, 5.6) • Compulsory, capacity, conflict misses – know defs. • Know all miss reduction techniques except forcompiler optimizations (blocking, etc.)

  11. Key Chapter 5 topics, cont. • Miss Penalty Reduction Techniques (5.4,5.6) • Hit Time Reduction Techniques (5.7) • Main memory (5.8-5.9) • bandwidth, latency, RAS/CAS • techniques for increased bandwidth • Technology & trends (5.9) • Virtual memory (5.10, 5.11) • Translation lookaside buffers. • Skip 5.12-5.18.

  12. Key Chapter 6 topics Multiprocessing • Intro (6.1-6.2) • SISD/SIMD/MIMD • Centralized vs. distributed shared-memory vs. message-passing • Communication models, performance • Parallelizability, cost-efficiency of multiprocessing • See Lecs. 35-36, q#8 on Fall ’01 final & sample final • Symmetric shared memory (6.3) • Write-invalidate cache coherence protocol (6.3) • Skip rest of ch. 6 (6.4-6.16)

  13. Key Chapter 7 topics Storage & I/O • Types of devices, terminology, performance, density (7.2) • I/O bus characteristics (7.3) • Reliability, Availability, Dependability (7.4) • RAID – Redundant Arrays of Inexpensive Disks (7.5) • Skip rest of ch. 7

  14. Key Chapter 8 topics Networks • Intro/simple network (8.1,8.2) • SAN/LAN/WAN • message formats • BW, time of flight, transmission time, transport latency, sender/receiver overhead, total latency • Network media (8.4) • know the terminology: cat5, twisted pair • Interconnection network topologies (8.5) • shared vs. switched media • toplogies: fat-tree, ring, mesh, hybercube • Which are scalable? (Lec.37, Fall ’01 final q.#8) • Network examples (8.7) - Know terms

  15. Good Luck! My office hours are 3:30-5 pm MW this week in case you have questions. Also, ask them via email.

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