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Operating Systems {week 14b}

Rensselaer Polytechnic Institute CSC 432 – Operating Systems David Goldschmidt, Ph.D. Operating Systems {week 14b}. Hierarchical storage architecture. very fast. very small. volatile. non-volatile. very slow. very large. Main memory (i).

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Operating Systems {week 14b}

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  1. Rensselaer Polytechnic Institute CSC 432 – Operating Systems David Goldschmidt, Ph.D. Operating Systems{week 14b}

  2. Hierarchical storage architecture very fast very small volatile non-volatile very slow very large

  3. Main memory (i) • Locations in memoryare identified bymemory addresses • When compiled, programsconsist of relocatable code • Other compiled modulesalso consist ofrelocatable code symbolic addresses in source code relative addresses in object code

  4. Main memory (ii) • At load time, anyadditional librariesalso consist ofrelocatable code physical addresses generated by loader

  5. Main memory (iii) • At run time, memoryaddresses of all objectfiles are mapped to asingle memory spacein physical memory

  6. Contiguous memory allocation • A pair of base and limitregisters define thelogical address space • Also known asrelocation registers

  7. OS OS OS OS Process 5 Process 5 Process 5 Process 5 Process 9 Process 9 Process 8 Process 1 Process 2 Process 2 Process 2 Process 2 Dynamic partitioning • Variable-length or dynamic partitions: • When a new process enters the system, the process is allocated to a single contiguous block • The operating system maintains a list of allocated partitions and free partitions

  8. Placement algorithms • How can we place new process Pi in memory? • First-fit algorithm: allocate the first free blockthat’s large enough to accommodate Pi • Best-fit algorithm: allocate thesmallest free block that’s largeenough to accommodate Pi • Next-fit algorithm: allocate thenext free block, searching from last allocated block • Worst-fit algorithm: allocate the largest free blockthat’s large enough to accommodate Pi

  9. OS Process 5 Process 8 Process 3 Process 2 Process 6 Process 7 Process 12 Fragmentation • Memory is wasted due to fragmentation,which can cause performance issues • Internal fragmentation is wasted memorywithina partition or process memory • External fragmentation can reducethe number of runnable processes • Total memory space exists to satisfya memory request, but memory isnot contiguous Process 9

  10. Noncontiguous allocation (i) • A noncontiguous memory allocation scheme avoids the external fragmentation problem • Slice up physical memory intofixed-sized blocks called frames • Sizes are powers of 2 (e.g. 214) • Slice up logical memory intofixed-sized blocks called pages • Allocate pages into frames • Note that frame size equals page size

  11. process Pi == in use main memory == free Noncontiguous allocation (ii) • When a process of size n pages is ready to run, operating system finds n free frames • The OS keepstrack of pagesvia a page table

  12. Paging via a page table (i) • Page tables map logical memoryaddresses to physical memoryaddresses

  13. Paging via a page table (ii) • Example process Pineeds 16MB oflogical memory • Page size is 4MB • Logical memory ismapped to a 32MBphysical memory • Frame size is 4MB binary 0 ==> 000000 4 ==> 000100 8 ==> 001000 12 ==> 001100 16 ==> 010000 20 ==> 010100 24 ==> 011000 28 ==> 011100

  14. Allocating a new process

  15. page offset page number p d Address translation (i) • Every logical address issliced into two distinctcomponents: • Page number (p): used as an index into thepage table to obtain the base physical memory address • Page offset (d): combined with the base address to identify the physical memory address

  16. page offset page number p d Address translation (ii) • Covers a logical addressspace of size 2m withpage size 2n (m – n) (n)

  17. Address translation (iii)

  18. Address translation (iv) • The page table is in main memory • Every memory access request actually requires two memory accesses: 2 1

  19. Translation look-aside buffer • Use page tablecaching at thehardware levelto speed addresstranslation • Hardware-leveltranslation look-aside buffer(TLB)

  20. Effective memory access time • Given: • Memory access time is 100 nanoseconds • TLB access time is 20 nanoseconds • TLB hit ratio is 80% • The effective memory-access time (EMAT) is • 0.80 x 120 ns + 0.20 x 220 ns = 140 ns • What is the effective memory-access timegiven a hit ratio of 99%? 50%?

  21. Multilevel page tables • For large page tables, usemultiple page table levels • Slice up the logical addressinto multiple page indicators

  22. Swapping • Processes in the ready queue have memory images waiting on disk • Processes are swapped in andout of memory • Can suffer from slow data transfer times

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