CS 105 Digital Logic Design

1. Chapter 4 Combinational Logic CS 105Digital Logic Design

2. Outline • 4.1 Introduction. • 4.2 Combinational Circuits. • 4.3 Analysis Procedure. • 4.4 Design Procedure. • 4.5 Binary Adder-Subtractor. • 4.6 Decimal Adder. • 4.7 Binary Multiplier. • 4.9 Decoders. • 4.10 Encoders. • 4.11 Multiplexers.

3. 4.1 Introduction (1-2) • Logic circuits for digital systems may be combinational or sequential. Combinational Circuit • Consists of logic gates whose outputs at any time are determined from only the present combination of inputs. • Performs an operation that can be specified logicallyby a set of Boolean functions.

4. 4.1 Introduction (2-2) Sequential Circuit • Employs storage elements in addition to logic gates. • Their outputs area function of the inputs and the state of the storage elements. • Because the state of the storage elements is a function of previous inputs, the outputs of a sequential circuit depend not only on present value of inputs, but also on past inputs.

5. 4.2 Combinational Circuit (1-2) Input Variables Consists of: Logic Gates Output Variables Transforms input data into required output data. Combinational circuits m outputs n inputs . . . . Block diagram

6. 4.2 Combinational Circuit (2-2) • n input variables  2n binary input combinations. • Each possible combination  one possible combination output. • Combinational circuit can be specified withtruth table. • Combinational circuit can be described by m Boolean functions. • Each output function is expressed in terms of the n input variables. Standard Combination Circuits • Adders, subtractors, comparators, decoders, encoders and multiplexers

7. 4.3 Analysis Procedure (1-4) • Determine the function that the circuit implements from a logic diagram. • Circuit’s function can be determined by either Booleanfunction or truth table. Steps • Make sure that it is combinational not sequential. • No memory elements. • No feedback path (feedback path: a connection from the output of one gate to the input of a second gate that forms part of the input to the first gate). • Obtain Boolean function or the truth table.

8. 4.3 Analysis Procedure (2-4) Boolean function

9. 4.3 Analysis Procedure (4-4) Truth Table

10. 4.4 Design Procedure (1-7) Steps • State the problem. • From the specifications of the circuit, determine the required number of inputs and outputs and assign a symbol to each. • Derive the truth table that defines the requiredrelationship between inputs and outputs. • Obtain the simplified Boolean functions for each output as a function of the input variables. • Draw the logic diagram and verify the correctness of the design

11. 4.4 Design Procedure (2-7) Example • Design a circuit that converts binary coded decimal (BCD) to the excess-3code for the decimal digits. Inputs Outputs • BCD (4 bits). • 4 inputs. • Symbols: A, B, C, D. • Ex-3 (4 bits). • 4 outputs. • Symbols: w, x, y, z.

12. 4.4 Design Procedure (7-7) Logic Diagram

13. 4-5 Binary Adder-Subtractor (1-20) Binary Adder-Subtractor • Is a combinational circuit that performs the arithmetic operations of addition and subtraction with binary numbers.

14. 4-5 Binary Adder-Subtractor (2-20) Half adder • Is a combinational circuit that performs the addition of two bits. Elementary Operations 0 + 0 = 0 ; 0 + 1 = 1 ; 1 + 0 = 1 ; 1+ 1 = 10 Truth Table • two inputvariables • x, y. • two outputvariables. • C (output carry), S (least significant bit of the sum).

15. 4-5 Binary Adder-Subtractor (3-20) Half adder Simplified Boolean Function (Sum of Products) Logic Diagram (Sum of Products) • S = x'y+xy' • C = xy

16. 4-5 Binary Adder-Subtractor (4-20) Half adder Logic Diagram (XOR and AND gates) Simplified Boolean Function (XOR and AND gates) • S=xÅ y • C = xy

17. 4-5 Binary Adder-Subtractor (5-20) Functional Block: Full-Adder • It is a combinational circuit that performs the arithmetic sum of three bits (two significant bits and previous carry). • It is similar to a half adder, but includes a carry-in bit from lower stages. • Two half adders can be employed to implement a full adder. Inputs & Outputs • Three input bits: • x, y : two significant bits • Z : the carry bit from the previous lower significant bit. • Two output variables: • C (output carry), S (least significant bit in sum).

18. Z 0 0 0 0 X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 0 0 1 0 1 1 0 Z 1 1 1 1 X 0 0 1 1 + Y + 0 + 1 + 0 + 1 C S 0 1 1 0 1 0 1 1 4-5 Binary Adder-Subtractor (6-20) Functional Block: Full-Adder • For a carry-in (Z) of 0, it is the same as the half-adder: • For a carry- in(Z) of 1: Operations

19. 4-6Decimal Adder (1-4) BCD Adder • Add two BCD‘s: • 9 inputs: two BCD's and one carry-in. • 5 outputs: one BCD and one carry-out. • Design approaches • Use unary full Adders. • A truth table with 29 entries • Each input digit does not exceed 9. • The output sum connot be greater than 9. • e.g. 9 + 9 + 1 =19 , the 1 in sum being an input carry. • The output of the binay sum must be represented in BCD.

20. 4-6Decimal Adder (2-4) BCD Adder Truth Table

21. 4-6Decimal Adder (4-4) BCD Adder Logic Diagram

22. 4-7Binary Multiplier (1-4) Multiplication of binary numbers is performed in the same way of decimal numbers. Example • Consider the multiplication of two 2-bit numbers. • Multiplicand bits are B0 and B1. • Multiplier bits are A0 and A1. • The product is C3C2C1C0.

23. 4-7Binary Multiplier (2-4) Logic Diagram • The partial product can be implemented with AND gates. • The two partial products are added with two half-adder (HA) circuits.

24. 4-7Binary Multiplier (3-4) J-Bit by K-BitBinary Multiplier • For J multiplier bits and K multiplicand bits to produce J + K bits , we need : • J x K AND gates. • (J-1) K-bit adders. Example (4-Bit by 3-Bit Multiplier) • Multiplicand : B3B2B1B0 • Multiplier: A2A1A0 • 12 AND gates • 2 four-bit adders. • Produces product of 7 bits

25. 4-7Binary Multiplier (4-4) Example (4-Bit by 3-Bit Multiplier)

26. 4-9Decoder (1-16) • Discrete quantities of information are represented in digital systems by binary codes. • A binary code of n bits is capable of representing up to 2ndistinct elements of coded information. Decoder • Is a combinational circuit that converts the binary information from n input lines to a maximum of 2nunique outputlines. • If the n-bitcoded information has unused combinations, thedecoder may have fewer than 2n outputs. • Called n-to-m-line decode, where m <= 2nminterms of n input variables.

27. 4-9Decoder (2-16) Example Consider three-to-eight-line decoder circuit • Inputs = 3. • Outputs = 8 (minterms) Example: Binary – to –octal decoder ONLY one output can be active at any time Truth Table

28. 4-9Decoder (3-16) Logic Diagram

29. 4-9Decoder (4-16) NAND gates Generates decoder mintermsin their complemented form

30. 4-9Decoder (5-16) Demultiplixers • A decoder with one or more enable (E) inputs. • Controlthe circuit operation. • E =0, Decoder is disabled. • E =1, Decoder is enabled. • A circuit that receives informationfrom a single Line and directs it to oneof 2npossible output lines.

31. 4-9Decoder (6-16) Demultiplixers Design a two-to-four-line decoder with an enable input. Truth table Uncomplemented output

32. 4-9Decoder (7-16) Demultiplixers Design a two-to-four-line decoder with an enable input. Logic Diagram

33. 4-9Decoder (8-16) Demultiplixers Design a two-to-four-line decoder with an enable input constructed with NAND gates. Truth table Complemented output

34. 4-9Decoder (9-16) Demultiplixers Design a two-to-four-line decoder with an enable input constructed with NAND gates. Logic Diagram

35. 4-9Decoder (10-16) Demultiplixers Design a 4-to-16 decoder. Design a 4-to-16 decoder using two 3-to-8 decoders.

36. A0 A1 A2 3-8-line Decoder D0 – D7 E 3-8-line Decoder D8 – D15 A3 A4 E 2-4-line Decoder 3-8-line Decoder D16 – D23 E 3-8-line Decoder D24 – D31 E 4-9Decoder (12-16) Demultiplixers Design a 5-to-32 line decoder using four3-to-8 line decoders with enable inputs and a 2-to-4 line decoder.

37. 4-9Decoder (13-16) Combinational Logic Implementation • Each output = minterm. • Implementing Boolean function (expressed in sum of minterms) by using: • A decoder . • An external OR gate. • Any combinational circuit with n inputs and moutputs can be implemented with an n-to-2n-linedecoder and m OR gates.

38. 4-9Decoder (14-16) Combinational Logic Implementation Design a full adder using a decoder.

39. 4-10Encoder (1-7) • Is a digital circuit that performs the inverse operation of a decoder. • An encoder has 2n(or fewer) input lines and n output lines. Example Design an octal-binary encoder

40. 4-10Encoder (2-7) Example Design an octal-binary encoder

41. 4-10Encoder (3-7) Limitations on previous example • If two inputs are active simultaneously, the output produces an undefined combination. • E.g. if D3and D6 are 1 simultaneously, the output of the encoder will be 111. • Resolvethis ambiguity, establish an input priority to ensure. D6 will be the higher priority. • Output with all 0's is generated when: • All the inputs are 0 • D0 is equal to 1. • Resolve by providing one more output to indicate whether at least one input is equal to 1.

42. 4-10Encoder (4-7) Priority Encoder • Is an encodercircuit that includes the priority function. • Resolve the ambiguity of illegalinputs. • if two or more inputs areequal o 1 at the same time. the input having the highestpriority will take precedence.

43. 4-10Encoder (5-7) Priority Encoder Design an four –to - two priority encoder

44. 4-11Multiplexer (1-15) • is a combinational circuit that selects a binary information from one of many input lines and directs it to a single output line. • The selection of a particular input line is contro1led by a set of selection lines. • 2ninput lines and n selection lines whose bit combinations determine which input is selected. • Also called a data selector, since it selects oneof many inputs and steers the binary information to the output line. • The sizeof a multiplexer is specified by the number 2n of its data input lines and the single output line.

45. 4-11 Multiplexer (2-15) Example Design a 2 –to-1 line MUX Function Table • Data Inputs = 21=1 • Selection Input= 1 • Output = 1

46. 4-11 Multiplexer (3-15) Example Design a 4 –to-1 line MUX Function Table • Data Inputs = 22 =4 • Selection Input= 2 • Output = 1

47. 4-11 Multiplexer (4-15) Example Design a 4 –to-1 line MUX

48. 4-11 Multiplexer (5-15) Notes • 2n – to – 1 MUX can be implemented using decoder: • Decode selection input lines. • n (selection input lines) – to - 2n decoder. • Adding the 2n input lines to each AND gate. • OR all AND gates. • An enable input (an option). • Multiplexers may have an enable input to control the operation of the unit • When the enable input is in the inactivestate, the outputs are disabled. • When it is in the active state, the circuit functions as a normalmultiplexer.

49. 4-11 Multiplexer (6-15) Example Design an 8–to-1 line MUX using a 3-to-8 line decoder.

50. 4-11 Multiplexer (7-15) Multiple bit Selection • Multiplexer circuits can be combined with common selection inputs to provide multiple-bit selection logic. • E.g. quadruple 2-to-1 line MUX.