Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849

1. ISVLSI 09 Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations Jins Davis Alexander Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, Auburn, AL 36849 Presented at the IEEE Computer Society Annual Symposium on VLSI Tampa, Florida, May 13-15, 2009

2. ISVLSI 09 Components of Power • Dynamic • Signal transitions • Logic activity • Glitches • Short-circuit • Static • Leakage Ptotal = Pdyn + Pstat = Ptran +Psc + Pstat

3. ISVLSI 09 Power Per Transition isc VDD Dynamic Power = CLVDD2/2+ Psc R Vo Vi CL R Ground

4. ISVLSI 09 Number of Transitions

5. ISVLSI 09 Outline • Motivation and Problem Statement • Background • Contributions: A New Dynamic Power Analysis Algorithm • Bounded Delays and Ambiguity Intervals • Maximum Transitions • Minimum Transitions • Simulation and Power Estimation • Experimental Results and Observations • Conclusion

6. ISVLSI 09 Problem Statement and Motivation • Problem - Estimate dynamic power consumed in a CMOS circuit for: • A set of input vectors • Delays subjected to process variation (typical in nanoscale technologies) • Challenge - Existing method, Monte Carlo simulation, is expensive. • Find a lower cost solution.

7. ISVLSI 09 Background • Bounded delay model is used to address process variations in logic level simulation and timing analysis. See references in the paper. • We model delay uncertainties by assigning each gate lower and upper bounds on its delay. These are known as min–max delays. • The bounds are obtained by adding specified process-related variation to the nominal gate delay for the technology.

8. ISVLSI 09 References • J. D. Alexander, Simulation Based Power Estimation for Digital CMOS Technologies, Master’s Thesis, Auburn University, December 2008. • J. D. Alexander and V. D. Agrawal, “Computing Bounds on Dynamic Power Using Fast Zero-Delay Logic Simulation,” Proc. 41st IEEE Southeastern Symp. System Theory, March 2009, pp. 107-112. Paper describes simulation algorithm and results. • This paper: Theoretical foundation – theorems on ambiguity propagation and maximum and minimum transitions – make the fast zero-delay analysis possible.

9. ISVLSI 09 Ambiguity Intervals IV FV IV FV EA LS EA LS • EA is the earliest arrival time • LS is the latest stabilization time • IV is the initial signal value • FV is the final signal value EAsv=-∞ LSsv=∞ EAdv LSdv EAdv=-∞ LSdv=∞ EAsv LSsv

10. ISVLSI 09 Propagating Ambiguity Intervals through Gates The ambiguity interval (EA,LS) for a gate output is determined by: • Ambiguity intervals of input signals. • Pre-transition and Post-transition steady-state values. • Min-Max gate delays. (mindel, maxdel)‏

11. ISVLSI 09 Representative Formulae • To evaluate the output of a gate, we analyze inputs i:

12. ISVLSI 09 Theorem 1: Propagating Ambiguity Intervals • Ambiguity interval at a gate output is: where the inertial delay of the gate is bounded as (mindel, maxdel).

13. ISVLSI 09 Finding Number of Transitions 3 14 7 10 12 14 2 5 8 10 12 [mintran,maxtran] [0,2] 3 14 (mindel, maxdel)‏ 6 17 1,3 EA LS EA LS [0,4] 5 17 EA LS where mintran is the minimum number of transitions and maxtran the maximum number of transitions.

14. ISVLSI 09 Theorem 2: Maximum Transitions • First upper bound: We calculate the maximum transitions (Nd) that can be accommodated in the ambiguity interval given by the gate delay bounds and the (IV,FV) output values. • Second upper bound: We take the sum of the input transitions (N) as the output cannot exceed this. We modify this by : N = N – k where k = 0, 1, or 2 for a 2-input gate and is determined by the ambiguity regions and (IV, FV) values of inputs. • The maximum number of transitions is lower of the two upper bounds: maxtran = min (Nd, N)

15. ISVLSI 09 Examples of maxtran (k = 0)‏ Nd = ∞ N = 8 maxtran=min (Nd, N) = 8 Nd = 6 N = 8 maxtran=min (Nd, N) = 6

16. ISVLSI 09 Example: maxtran With Non-Zero k [n1 = 6] [n1 + n2 – k = 8 ] , where k = 2 EA LS EAsv = - ∞ LSdv = ∞ EAdv LSsv [n2 = 4] EAsv = - ∞ LSdv = ∞ EAdv LSsv [ 6 ] [ 6 + 4 – 2 = 8 ] [ 4 ]

17. ISVLSI 09 Theorem 3: Minimum Transitions • First lower bound (Ns): Based on steady state values, i.e., 00, 11 as no transition and 01, 10 as a single transition. • Second lower bound (Ndet): The minimum number of transitions that can occur in the output ambiguity region is the number of deterministic signal changes that occur within the ambiguity region and such that signal changes are spaced at time intervals greater than or equal to the inertial delay of the gate. • The minimum number of transitions is the higher of the two lower bounds: mintran = max (Ns, Ndet)

18. ISVLSI 09 Example: mintran EA LS EAsv = - ∞ LSsv = ∞ EAdv LSdv d EAdv = - ∞ LSdv = ∞ (mindel, maxdel)‏ EAsv LSsv • There will always be a hazard in the output as long as (EAsv – LSdv) ≥maxdel • Thus in this case the mintran is not 0 as per the steady state condition, but is 2.

19. ISVLSI 09 Power Analysis Algorithm • maxdel, mindel = nominal delay ± Δ% • Three linear-time passes for each input vector: • First pass: zero delay simulation to determine initial and final values, IV and FV, for all signals. • Second pass: determines earliest arrival (EA) and latest stabilization (LS) from IV, FV values and bounded gate delays. • Third pass: determines upper and lower bounds, maxtran and mintran, for all gates from the above information.

20. ISVLSI 09 Simulation Setup • Standard gate delay 100 ps. • Wire-load model used; gate proportional to fan–out. • The power distribution determined for 1000 random vectors with a vector period of 10000 ps. • For each vector pair, 1000 sample circuits were simulated.

21. ISVLSI 09 Maximum Power • Monte Carlo Simulation vs. Min-Max analysis for circuit C880. 100 sample circuits with + 20 % variation were simulated for each vector pair (100 random vectors). R2 is coefficient of determination, equals 1.0 for ideal fit.

22. ISVLSI 09 Minimum Power R2 is coefficient of determination, equals 1.0 for ideal fit.

23. ISVLSI 09 Average Power R2 is coefficient of determination, equals 1.0 for ideal fit.

24. ISVLSI 09 C880: Monte Carlo vs. Bounded Delay Analysis 1000 Random Vectors, 1000 Sample Circuits

25. ISVLSI 09 C2670: Effect of Inertial Delay • Transition Statistics for high activity gate 1407 in c2670 for a random vector pair. Histograms obtained from Monte Carlo Simulations of 100 sample circuits. mintran = 0 maxtran = 8 maxtran =1 0 mintran = 0

26. ISVLSI 09 Effect of Inertial Delay… mintran = 0 mintran = 0 maxtran = 6 maxtran = 4

27. ISVLSI 09 Power Estimation Results • Circuits implemented using TSMC025 2.5V CMOS library , with standard size gate delay of 10 ps and a vector period of 1000 ps. Min-Max values obtained by assuming ± 20 % variation. The simulations were run on a UNIX operating system using a Intel Duo Core processor with 2 GB RAM.

28. ISVLSI 09 Zero-Delay Vs. Event-Driven Simulation

29. ISVLSI 09 Conclusion • Bounded delay model allows power estimation method with consideration of uncertainties in delays. • Analysis has a linear time complexity in number of gates and is an efficient alternative to the Monte Carlo analysis. • Monte Carlo versus min-max analysis: Reduced dimension of sample space - Monte Carlo is over vectors and circuits;min-max is over vectors only. • Future work: (a) Find number of vectors for convergence of result; (b) find probability distribution of power.

30. ISVLSI 09