System Programming

NFC-IET-2011 System Programming Lecture-06 Interrupt Mechanism-Microprocessor Signals Dated: April 04, 2011 By Somia Razzaq Note: Some slides and images of following lecture are taken from VU

Microprocessor Signals • Microprocessor package has many signals for data, control and addresses • Some of these signals may be input signals and some might be output • Hardware interrupts make use of two of such input signals namely • NMI (Non Maskable Interrupt) & • INTR(Interrupt Request)

Reset Microprocessor Hold NMI INTR

Hardware Interrupt and Arbitration • Most of the devices use the INTR line like COM ports, LPT ports, keyboard, timer etc • NMI signal is used by devices which perform operations of the utmost need like the division by zero interrupt which is generated by ALU circuitry which performs division. Definitely this operation is not possible and the circuitry generates an interrupt if it receives a 0 as divisor from the control unit • Only one signal is available for microprocessor interruption, this signal is arbitrated among various devices • This arbitration can be performed by a special hardware called the Programmable Interrupt Controller (PIC)

Programmable Interrupt Controller • A single programmable interrupt controller (PIC) device can arbitrate among 8 different devices. It has 8 inputs IRQ0-IRQ7 • RQ0 has the highest priority and IRQ7 has the lowest • Each IRQ input is attached to an I/O device whenever the device requires an I/O operation it sends a signal to the PIC • The PIC on the basis of its priority and presence of other requests decides which request to serve

Programmable Interrupt Controller D0 IRQ0 PIC IRQ1 D1 IRQ2 D2 D7 IRQ7 INT

Interfacing of PIC with Microprocessor • Whenever a request is to be served by PIC, it interrupts the processor with the INT output connected to the INTR input of the processor and send the interrupt # to be generated by data lines connected to the lower 8 datalines of the data bus to inform the processor about the interrupt number • In case no higher priority signal is available to the processor and the processor is successfully interrupted the microprocessor sends back an INTA (interrupt Acknowledge) signal to inform the PIC that the processor has been interrupted

Interval Timer PIC 0 IRQ1 KBD Controller 1 D0 2 MICRO PROCESSOR COM2 3 D7 COM1 4 INT INTR 5 Other Controllers INTA 6 Printer Controller IRQ7 7 D1

Cascading Programmable Interrupt Controller • In standard PCs there may be more than 8 devices so generally two PIC are used for INTR line arbitration • These 2 PICs are cascaded such that they collectively are able to arbitrate among 16 devices in all as shown in fig. in next slide • The PICs are cascaded such that a total of 16 IRQ levels can be provided number IRQ0-IRQ15 • IRQ level 2 is used to cascade both of the PIC devices • The Data lines are multiplexed such that the interrupt number is issued by the concerned PIC • The IRQ 2 input of the Master PIC is connected to the INT output of the Slave PIC

If the slave PIC is interrupted by a device, its request is propagated to the master PIC and the master PIC ultimately interrupts the processor on INTR line according to the priorities • In a standard PC the PICs are programmed such that the master PIC generated the interrupt number 8-FH for IRQ0 –IRQ7 respectively and the slave PIC generates interrupt number 70-77H for IRQ8-IRQ15

MASTER D0 IRQ0 PIC IRQ2 IRQ7 D7 cas1 INTR INT cas2 cas3 INTA D0 IRQ8 PIC D7 IRQ15 cas1 INT cas2 INTA cas3 SLAVE

Priority Level • IRQ0 = HIGHEST • IRQ15 = LOWEST • If a number of requests are available instantaneously(at once) the request with higher priority will be sent for service first by the PIC

Hardware Interrupt are Non-Preemptive • What will happen if a lower priority interrupt is being service and a higher priority interrupt request occurs, will the lower priority interrupt be preempted? • The answer is that the interrupt being serviced will not be preempted no matter what. • The reason for this non-preemptive can be understood by the example illustrated as follows

If Hardware Interrupt are Preemptive E.g. KBD Interrupt C PRESSED A PRESSED B PRESSED Input received C B A Logically Incorrect Logically Correct A B C

So for diagram should be A PRESSED B PRESSED C PRESSED Input received A B C Logically Correct

Who Notifies EOI(End of Interrupt)? • The PIC has to be notified about the return of the previous interrupt by the ISR routine • From programmer point of view this is the major difference between H/W and software interrupt • A software interrupt will not require any such notification • As the diagram in next slide illustrates that every interrupt returns with an IRET instruction. This instruction is executed by the microprocessor and has no linkage with the PIC • So there has to be a different method to notify the PIC about the End of interrupt

Flow Diagram for Normal Interrupt INPUT/OUTPUT Operations IRET

Pending Hardware interrupts • While a hardware interrupt is being processed a number of various other interrupt maybe pending • . For the subtle working of the system it is necessary for the In-service hardware interrupt to return early and notify the PIC on return • If this operation takes long and the pending interrupt requests occur repeated there is a chance of loosing data

Programming the PIC To understand how the PIC is notified about the end of interrupt ,lets take a look into the internal registers of PIC and their significance

ICW = Initialization Control Words OCW = Operation Control Words • ICW programmed at time of boot up • ICW are used to program the operation mode like cascade mode or not, also it is used to program the function of PIC i.e. if it is to invoke interrupts 08~ 0FH or 70-77H on IRQ request. • OCW are used at run-time. • OCW is used to signal PIC, EOI code. • OCW are also used to read/write the value of ISR(In-service register), IMR(interrupt mask register), IRR(interrupt request register)

7 6 5 4 3 2 1 0 ISR 7 6 5 4 3 2 1 0 IMR 7 6 5 4 3 2 1 0 IRR

Master PIC has two ports 20H=OCW for EOI 21H=OCW for IMR • Slave PIC has two ports as well AOH=OCW for EOI code A1H=OCW for IMR

#include <dos.h> #include <stdio.h>#include <bios.h>void main(){outport(0x21,0x02);}

#include <dos.h> #include <stdio.h>#include <bios.h>void interrupt(*oldints)();void interrupt newint8();void main(){ oldints = getvect(0x08); setvect(0x08,newint8); keep(0,1000);}

void interrupt newint8(){ t++; if (t==182) { outport(0x21,2); } else { if (t==364) { outport(0x21,0); t=0; } } *oldints();}

#include <dos.h> void interrupt(*old)();void interrupt newint9();void main(){ old = getvect(0x09); setvect(0x09,newint9); keep(0,1000);}void interrupt newint9(){ if (inportb(0x60)==0x1F) { outportb(0x20,0x20); return; } (*old)();}

#include <dos.h> void interrupt(*old)();void interrupt newint9();int i=1;void main(){old=getvect(0x09);setvect(0x09,newint9);keep(0,1000);} void interrupt newint9(){if (inportb(0x60)==0x1F) { i++; if (i<=5){ outportb(0x20,0x20); return; } i=1; } (*old)();}

#include <dos.h> void interrupt(*old)();void interrupt newint9();char far *scr=(char far *) 0x00400017;void main(){ old=getvect(0x09); setvect(0x09,newint9); keep(0,1000);}void interrupt newint9(){ if((inportb(0x60)==83)&&((*scr)&12==12)) { outportb(0x20,0x20); return; } (*old)();}

System Programming