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Suming Lai, Boyuan Yan and Peng Li Department of Electrical and Computer Engineering

Stability Assurance and Design Optimization of Large Power Delivery Networks with Multiple On-Chip Voltage Regulators. Suming Lai, Boyuan Yan and Peng Li Department of Electrical and Computer Engineering Texas A&M University { laisuming , byan , pli } @ tamu.edu.

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Suming Lai, Boyuan Yan and Peng Li Department of Electrical and Computer Engineering

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  1. Stability Assurance and Design Optimization of Large Power Delivery Networks with Multiple On-Chip Voltage Regulators Suming Lai, Boyuan Yan and Peng Li Department of Electrical and Computer Engineering Texas A&M University {laisuming, byan, pli} @ tamu.edu

  2. Low Power and Power Delivery Design Trends Current WireSizing/DecapInsertion Vcc On-chip Power Grids ~10-100 million nodes PCB/Package Design [source: Ansys] [ITRS 2011] On-Chip Voltage Regulation: A Significant Current Trend [El-Nozahi et al., JSSC, 2010] [Guo et al., JSSC, 2010] [Hazucha et al./Intel JSSC, 2005]

  3. Moving Towards Distributed On-Chip Voltage Regulation Benefits in Supply Noise and Efficiency [Zenget al., DAC, 2010] A Network of Micro-Regulators Recent Industrial Demonstration [Bulzacchelli et al. IBM/JSSC, 2012]

  4. Design Management Challenge Regulator Design Power Grids Design Amp • Gain • Bandwidth • Bias Current • Phase Margin • Noise • Load • … • IR Drop • Decap insertion • Wire Sizing • Package • DFM • … Integrate LDOs with the grids Stability?? DecoupledDesign Still Very Desirable! Analog Design Team Physical Design Team

  5. Analog Designer’s View of Stability • Phase Margin • How does it work? • Target one loop • Single input/single output • Lump load (capacitor) • Reality: • Loops between LDOs • Distributive load network

  6. “Analog Designer’s”Approach to PDN Stability • Come up a ‘stable’ LDO w/ a lump load (~120º phase margin) • Hope it will work for the network Load Current Global VDD Grids Quickly Settled Pole Movements LDO LDO LDO LDO Slightly Fluctuate Regulated Grids Heavily Oscillate Global GND Grids PCB & Pckg

  7. Why Doesn’t It Work? • Multiple regulators in the network • Complex interactions between active regulators and distributed load (lots of loops) • Complex interactions between different regulators (lots of loops) Global VDD Grids Global GND Grids Regulated Grids LDO LDO LDO … Pckg & PCB

  8. “Numerical Analyst’s” Approach: Pole Analysis • Treat the PDN as a whole • Perform exhaustive • pole/eigenvalue analysis(cubic cost) • Too costly • for typical PDNs • Even more intractable if LDO design is iterated

  9. Proposed Work • Goals • Feasible checking of network stability • Feasible stability-ensuring LDO design with network stability • Localized checking and design methodologies • How • Develop Hybrid Stability Theory for PDNs with distributed regulation • New (localized) Hybrid Stability Margin (HSM) for regulator design • Efficient stability checking method • Largely separated design methodology • LDO design with minimum load information • Regulator design implications and design exploration • Identify key design parameters/knobs for achieving HSM • Identify LDO topology dependency and new design technique • Tradeoffs with other performances

  10. Basic Theoretical Approach • Partitioning and modeling • Separate LDOs from the passive loads • Use MIMO modeling for both parts • Expose key network-level interactions and loops • Key system properties for ensuring stability • Small-Gain network-level loops • Passivity  both passive loads & active regulators • Counterintuitive for analog design but it works … • Hybrid Stability Theory • Combine Small-Gain & Passivity • Provide more flexibility and reduce pessimism

  11. Our Network Modeling Strategy G Block: Spatially spread LDOs H Block: RLCSub-Network PDNwih multiple LDOs

  12. Block Models • LDOs: Y-parameter model • RLC network: Z-parameter model V1 V2 Admittance Matrix of LDO Block Impedance Matrix of the RLC sub-network

  13. System Model for Stability Analysis RLC LDO RLC LDO

  14. System Concepts (1): Gain • L-2 gain, g • General definition: System output System input Inputs Outputs LTI systems: Maximum Possible Amplification

  15. Stability Approach #1: Small-Gain • How to stabilize the system by controlling the gain? • Small-Gain Theorem gH gH gGgH < 1 gG gG [V. D. Schaft, L2-gain and passivity techniques in nonlinear control. 2000]

  16. Problems? • Useful but a stringent condition • Over-constrains gain in practice • Issues with voltage regulation • RLC sub-network resonance: impedance peaking at mid/high frequencies • Must control LDO’s gain across the entire frequency gH gG Severe Load/Line Regulation Performance Degradation

  17. Can We Do It Differently? • Intuition: leverage Passivity • Can Active analog circuits be made Passive? • Designers do not usually think about it this way • Full Passivity can be practically hard or wasteful … If passive Network Stable! LDO Block Passive Network

  18. System Concepts (2): Passivity • Passive systems do not produce power • Strictly passive systems burn power • LTI system with transfer matrix Y is passive if strictlypassive ≥d >0

  19. Stability Approach #2: Passivity • Passivity theorem • Interconnection of Hand Gis stable, if they are passive, and at least one of them is strictlypassive [V. D. Schaft, L2-gain and passivity techniques in nonlinear control. 2000]

  20. Can Active Analog Circuit Look Passive? • A real study of LDO passivity • Not fully passive in general • Don’t want to be fully passive:No ‘active’ voltage regulation! • Define Local Passivity • Intuitive definition: • More formal definition: Exist d ≥0 and e ≥0, s.t. Realistic LDO Circuit[Lai/Li, AICSP’12] [Lai/Yan/Li,TCAD, submitted]

  21. Explore Local Passivity for Stability • Our design insights based on realistic LDO designs Frequency High Low Package Resonance LDO Bandwidth High Freq. • Impedance peaking due to package resonance • Force passivity of LDOs • Either gain or passivity • Not critical • Force loop gain <1 • High LDO gain • High RLC impedance • Apply repartitioning technique • Force loop gain <1 [Lai/Yan/Li,TCAD,Submitted]

  22. Stability Approach #3: General Hybrid Stability • The interconnection of two LTI systems H andGis stable, if at each frequency w • EitherH(jw)or G(jw)is passive and the other one is strictlypassive; (Passivity condition) • Loop gain(Gain condition) [Forbes et al., IET Control Theory and Application 2010]

  23. Stability Approach #3: Application to PDN • How to apply to our case • Practical RLC sub-network is strictlypassive • Rigorous proof PDN: Gain Condition Either Condition Passivity Strict Passivity ? RLC: Each port has a serial resistor [Lai/Yan/Li,TCAD, submitted]

  24. Localized Stability Checking – LDOs • Passivity check • Gain check G2nx2n = (Block Diagonal) AC analysis on individual LDOs!

  25. Localized Stability Checking – RLC Netowrk • Passivity check • Strictly passive, theoretically proved • No need to check • Gain check • One time AC analysis – frequency sweeping for • Routinely done by power grid/package designers • No need to re-run if LDOs are re-designed or tuned

  26. New Hybrid Stability Margin (HSM) • 2D passivity/gain space • LDOs: lmin(G) >0  passive • LDOs & RLC network: ||H(jw)||2||G(jw)||2< 1  small gain • Localized HSM for LDO design • Normalized Distance Measure to border of instability • Negative value means instability

  27. Localized Checking and Design Flow Tune LDO design Tune LDO design PG/Package Characterization AC Simulation AC Simulation F Check Phase Margin Check Hybrid Stability Margin F P P F Performance Check F Performance Check P P Finish Finish Old flow using PM Our flow using HSM

  28. HSM Design Implications (1) • Design freedom along the frequency axis • Choose either passivity condition or small-gain to satisfy HSM • Our findings • Key design knobs: • DC/low-frequency gain, UGF, output impedance, dominant pole • Choose one of the properties to minimize performance degradation and overhead: area/power Key Ckt Parameters: • Width of Mp • Width of M’p • Mc and Mdb • Cc1, Cc2, Cc3, and C1 Package Resonance LDO Bandwidth High Freq. • Small Gain (or Passivity) • Passivity • Small Gain

  29. HSM Design Implications (2) • Example: an effective way to control loop gain • |is| > |iEA| (no degradation on “physical” load/line regulation) New LDO Design Techniques • Add a small pull-down transistor to increase |is| • Change the topology of output stage to increase |is| Topology Dependency New Circuit

  30. Automated Design Optimization • LDO design topology • Key design knobs • Width of Mp • Width of M’p • Mc and Mdb • Cc1, Cc2, Cc3, and C1 • Joint Perform/Stability Nonlinear Opt. driven by HSM constraint [Lai & Li, AICSP’12] Tune |is|, good for HSM Tune HSM, Accuracy, Zoutand GBW Tune Pg Tunes GBW and HSM

  31. Verification using a Small PDN (1) • Resort to pole analysis for verification Pole Movements • Fixed/Optimized Design: • Stable • Initial LDO Design: • Phase Margin = 118° • Cause Network Instability

  32. Verification using a Small PDN (2) • Time-domain verification of network-level stability for the fixed/optimized design Stable

  33. Design for a 200K-Node PDN • Initial design phase margin = 118° • Loop gain/lmin as functions of frequency

  34. Time-Domain Network-Level Stability Check • Initial Design Sustained Oscillation!

  35. Optimized Design for the 200K-Node PDN • Fixed/optimized design • Loop gain/lmin as functions of frequency

  36. Time-Domain Network-Level StabilityCheck • Fixed/Optimized Design Voltage Settled!

  37. Runtime Efficiency • AC analysis of the passives • Frequency range: 1Hz to 1THz • Number of frequency samples (P): 2401 • Our in-house simulator takes: 11 hours • LDO design iteration • ~100 design iterations • LDO total optimization time: 116 minutes • Dominant Cost • One-time AC analysis of the passives

  38. Design Comparison & Tradeoffs • Design performances • DC regulation accuracy • Output Impedance (dynamic regulation accuracy) • Quiescent power (power efficiency under zero/light load) • Power utilization efficiency:Defined by output admittance () achieved per unit quiescent power consumption • Reference design • Manual design with the best FOM (figure of merits on performances) and a high phase margin • Compare with LDOs designed using our flow

  39. Design Comparison & Tradeoffs – Case 1 • Stability-ensuring design using HSM constraint and our flow • Performance optimization biased to output impedance

  40. Design Comparison & Tradeoffs – Case 2 • Stability-ensuring design using HSM constraint and our flow • Performance optimization biased to Quiescent Power

  41. Summary • (Distributed) on-chip voltage is a significant on-going design trend • Stability is a great challenge for power delivery networks with distributed voltage regulation • To address this challenge requires to bring together:theory, CAD and circuit design • Developed a hybrid-stability based localized stability checking & design methodology • Studied the circuit design implications of imposing new HSM constraint and the resulting stability/performance tradeoffs

  42. Thanks !! Q&A

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