File Management System Paper D4 - Supplement

1. 2002 MAPLD International Conference File Management System Paper D4 - Supplement • Ben Cohen (VhdlCohen Training/Consulting )vhdlcohen@aol.com vhdlcohen@klabs.org

2. File Management System Provides linked inter-relationships of • Documents (e.g., specifications, diagrams, timing models) • HDL designs (synthesizable and Testbench Models) • Simulation and synthesis result

3. REQUIREMENTS ARCHITECTURE/ IMPLEMENTATIONDOCUMENT REQUIREMENTS ARCHITECTURE/ IMPLEMENTATIONDOCUMENT REQUIREMENTS ARCHITECTURE/ IMPLEMENTATIONDOCUMENT PACKAGES SCRIPTS LIBRARIES ALGORITHMIC/ BEHAVIORAL HDL MODEL ALGORITHMIC/ BEHAVIORAL HDL MODEL SYTHESIZABLE HDL DESIGN ALGORITHMIC/ BEHAVIORAL HDL MODEL SYTHESIZABLE HDL DESIGN SYTHESIZABLE HDL DESIGN VERIFICATION PLAN VERIFICATION PLAN VERIFICATION PLAN APPLICATION HDL DESIGN TESTBENCH HDL DESIGN APPLICATION HDL DESIGN TESTBENCH HDL DESIGN APPLICATION HDL DESIGN OTHERDOCUMENTATION & SPECIFICATIONS TESTBENCH HDL DESIGN OTHERDOCUMENTATION & SPECIFICATIONS OTHERDOCUMENTATION & SPECIFICATIONS RESULTS, SCRIPTS ISSUES: Multitude of Inter-related Files!!!

4. VHDLDOC -- GNU TOOL • Automatically generates hyperlinked html-documentation of VHDL Code. • Hierarchy, Ports, Generics, Packages, Source code, Documents (e.g., requirements, plans), Images • The markup-language is like the one of JAVADOC. • Runs on Unix/Linux. • Results can be made compatible with windows with awk program File naming issue. (see next slide for fix). • Freely available at: http://schwick.home.cern.ch/schwick/vhdldoc/Welcome.html 

5. Awk script to convert html files to Windows compatible format In file fixhtml.awk FNR == 1 {file = FILENAME ; gsub( /::/, "__", file)}{gsub( /::/, "__" )gsub("%3A%3A", "__")print > file }to activate:awk -f fixhtml.awk * Where * refers to all generated html files

6. VHDLDOC html-pages Generated Output -- Header • Links to: • Index Alphabetical ordered list of all design entities in project • Annotated List lists all entities with their short description. • Hierachy Entities with all their architectures and the components instantiated therein. • Deep Hierachy Entities with their architectures and therein instantiated components recursively so that the whole design-hierachy is visible. • Package Packages found in the design files. • Files All parsed design files.

7. VHDLDOC ExampleUART and TB Model * Header Entities in Design * Code from book: Component Design by Example, 2001 isbn 0-9705394-0-1

8. Top Level Entity (1) Details on UART Entity

9. Top Level Entity (2) Contents not shown for brevity Footer

10. Top Level Entity (3) Links to Other Documents (e.g., specs, plans, etc.

11. Deep Design Hierarchy Links to Entity Link to Architecture

12. Deep Design Hierarchy

13. Package List – Links--

14. File Index Links to VHDL Files (shown in HTML)

15. Coding Style • Convention • Support file management style • Enhance code readability

16. Needed Conventions -- VHDLDOC Support style -- • One object declaration and statement per line • Entities, packages, architectures and processes MUST be named and the name MUST be repeated after the corresponding end-statement. • ENHANCES READABILITY • library ieee; • use ieee.std_logic_1164.all; • entity e is • generic ( • WIDTH : integer := 8; -- Bits/word • DEPTH : integer := 4); -- fifo depth • port ( -- typical 25-pin RS232 Connector • TXD : out std_logic; -- 2 TD --> Transmit Data • RXD : in std_logic; -- 3 RD <-- Receive Data • …); • end entity e; • architecture rtl of e is • begin -- architecture rtl • … • end architecture rtl; Note: GNU Emacs in Vhdl-Mode supports this notation automatically

17. VhdlDoc Mark-up Language

18. Example --*********************************************************** --* @short Title : UART top level for UART model --* Project : "Component Design by Example" --* @li UART FEATURES --* @li Parity option --* @li 1/2 stops --* @see Requirements: isbn 0-9705394-0-1 "UART Requirement Specification", ch 2 --* @see Architectural Plan, isbn 0-9705394-0-1 Architectural Plan, ch 4 --* @diagram uarttop.jpg Fig. 4 High Level View of UART --* File : uart.vhd --* @author : Ben Cohen <VhdlCohen@aol.com> --* Company : VhdlCohen Training and Consulting --* @date Created : 2000/08/15 --* @revision Last update: 2000/09/25 --* @generic Width_g : integer := 8; -- Bits/word --* @generic Depth_g : integer := 4; -- fifo depth --* @port TXD : out std_logic; -- 2 TD --> Transmit Data --* @port RXD : in std_logic; -- 3 RD <-- Receive Data --/