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A NEW 12-bits 40 MS/s, LOW-POWER, LOW-AREA PELINE ADC FOR VIDEO ANALOG FRONT ENDS

A NEW 12-bits 40 MS/s, LOW-POWER, LOW-AREA PELINE ADC FOR VIDEO ANALOG FRONT ENDS. 班級 : 積體所碩一 學生 : 林義傑. RCIM, Dept. of Electrical and Computer Engineering University of Windsor, Windsor, ON, N9B 3P4, Canada. Reference.

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A NEW 12-bits 40 MS/s, LOW-POWER, LOW-AREA PELINE ADC FOR VIDEO ANALOG FRONT ENDS

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  1. A NEW 12-bits 40 MS/s, LOW-POWER, LOW-AREA PELINE ADC FOR VIDEO ANALOG FRONT ENDS • 班級: 積體所碩一 • 學生:林義傑 RCIM, Dept. of Electrical and Computer Engineering University of Windsor, Windsor, ON, N9B 3P4, Canada

  2. Reference D. Dalton, G. Spalding, H. Reyhani, T. Murphy, K. Deevy, M. Walsh, and P. Griffin,“A 200-MSPS 6-Bit Flash ADC in 0.6-μ m CMOS,” IEEE Trans. On Circuits and Systems-II, vol. 45, no. 11, pp. 1433-1444, Nov., 1998.

  3. Outline • The common Pipeline ADC • The proposed pipeline Adc Archetecture • Measurement Results • Conclusion

  4. ADC應用頻率範圍及速度介紹 fs ≥ 2 fin

  5. Introduction common Pipeline ADC

  6. ADC工作模式 • Voltage-Mode • Current-Mode

  7. The proposed pipeline Adc Archetecture fs ≥ 2 fin

  8. Current-mode stage architecture

  9. Current-mode stage architecture

  10. Power dissipation and area of each stage

  11. Measurement Results SFDR=62.5dB SNDR=58.3dB

  12. Measurement Results

  13. Conclusions • The proposed ADC architecture has used a combination of current-mode and voltage-mode stages to significantly reduce both power dissipation and area

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