FPGA: Main frequency: 100MHz Rx / Tx Modules @ frequency of 115,200Hz

MATLAB GUI: Rx / Tx Via UART interface @ frequency of 115,200Hz • FPGA: • Main frequency: 100MHz • Rx / Tx Modules • @ frequency of 115,200Hz • ADS1928R: • Main frequency: 2.048MHz • SPI-Data Out freq’: >110KHz

General Wishbone packet 8 bits SOF 1 Byte Type 1 Byte Address 3 Byte Data Length 2 Bytes Data (Payload) Up to 1 KByte CRC 1 Byte EOF 1 Byte

Operation Commands (ex: RDATAC, Rreg, Wreg, Standby, Reset, ect’..) Optional: Second Byte for (Rreg, Wreg) and sample interval for RDATAC command. 1st Command Data for Wreg commands 2nd Command Additional Data

ECG Controller Wishbone Master Command Register Wishbone Slave Aux Register ECG FSM FIFO SPI Master

Rx Path din UART-Rx Message Pack Decoder Message Decoder to Wishbone Master Wishbone Master RAM CRC Wishbone Slave Error Register

Tx Path Message Pack Encoder UART-Tx Wishbone Master Message Decoder to Wishbone Master FIFO RAM CRC Wishbone Slave

RESET Command Req Wishbone Prolg Command Fetch Command Decode Idle RDATAC Intrvalreq Wead Register 2ndcmdreq Wakeup! Reset Rrite Register 2ndcmdreq StandBy Wakeup! Wead Register 2ndcmd fetch RDATAC interval req Read Register 2ndcmd fetch Wead Register 1stcmd RDATAC Interval retch Read Register 1stcmd Wead Register 2ndcmd RDATAC cmd Read Register 2ndcmd Wead Register - Write Values RDATAC Start Read Register - Read Values RDATAC Wishbone Start RDATAC Read Wishbone epilgrreg start RDATAC Wishbone Write RDATAC Stop Wishbone epilgrreg write SDATAC cmd Wishbone epilg RDATAC start Wishbone epilg RDATAC write

ECG Controller TB Remote Wishbone Slave ECG Controller Wishbone Master Data Input Command Register Wishbone Slave Aux Register ECG FSM FIFO SPI Master Remote SPI Slave SPI Slave FIFO

FPGA: Main frequency: 100MHz Rx / Tx Modules @ frequency of 115,200Hz