R&D for Embedded Analogue Testing

1. R&D for Embedded Analogue Testing Diego Vázquez García de la Vega Instituto de Microelectrónica de Sevilla (IMSE-CNM) dgarcia@imse.cnm.es

2. Outline • A panoramic view • Analogue and MS Test. Current Status • External Testing. Fundamental Problems • Solutions • Conclusions

3. A Panoramic View Application Specific Logic Glue Logic DSP ASIC (80’s) Processor Memory Memory Digital SoC (90’s) Wired Communication Wireless Communication Audio & Video MS SoC (00’s) RF circuitry Power Management Passive Components Next SOCs FROM ASICs to SOCs And… increased performance in terms of speed, bandwidth, accuracy, power, voltage supply, etc…

4. A Panoramic View uP Memory Mixed-SignalTester FunctionalTester MemoryTester LogicTester RFTester digital MixedSignal RF System-On-Board (SOB) • Dedicated technologies • Pre-tested ICs (dedicated tester) • Board level test

5. A Panoramic View uP Memory uP Memory digital digital RF MixedSignal MixedSignal RF System-On-Board (SOB) System-On-Chip (SOC) • Dedicated technologies • Pre-tested blocks • Board level test • Mixed technologies on the same chip • Pre-designed blocks (not tested) • Core and IC level Test required

6. A Panoramic View Std Blocks IP Blocks uP Memory Mixed-SignalTester FunctionalTester MemoryTester LogicTester RFTester digital RF MixedSignal System-On-Chip (SOC) Different cores with different modeling, different test requirements, different tester languages, etc.

7. A Panoramic View uP Memory digital RF MixedSignal Design and Test Development Manufacturing Test IP Core-Based System Design and Test Development Core provider IP-Core-Based approach • Core Provider may not know: • Which test method, tolerance • margins, etc. to use. • System integrator may have: • Very limited knowledge of the adopted core. • Test of embedded IP cores: • Joint responsibility of both core provider and system integrator. System integrator

8. A Panoramic View uP Memory digital RF MixedSignal Source: SIA Roadmap System-On-Chip (SOC) More to Test !!!!!

9. A Panoramic View uP Memory digital RF MixedSignal Source: SIA Roadmap System-On-Chip (SOC) Less Test Access !!!!!

10. A Panoramic View uP Memory digital RF MixedSignal Source: SIA Roadmap System-On-Chip (SOC) Increased Bandwidth !!!

11. Analogue and MS Test Current Status FUNCTIONAL TEST Specification-Based Test The Circuit Complies Specs Stimuli Generator CUT ResponseInterpreter I/O Behavior • The CUT is considered as a black box • All interesting I/O relationship must be checked out • Tests may overlap and be redundant • It takes long time • It requires different instrumentation • Tests do not guarantee defect-free ICs

12. Analog Circuit classes: Filters ADCs DACs PLLs RF Transceivers Signal Conditioners etc Testing methods is circuit dependent: Filters Frequency domain, Passband, Rejection band, Distortion, Dynamic Range, etc. Data Converters Time domain, Linearity (INL, DNL), SNR, ENB, etc. PLLs Frequency Domain, Stability, Capture Range, Jitter, etc. Basic Blocks (OTAs, Opamps, etc) DC, AC, Transient, etc. Analogue and MS Test Current Status • Combined into an IC requires different test techniques: • Test stimuli • Response analysis

13. Analogue and MS Test Current Status • Specification-based (functional) tests: Tractable and does not need an analog fault model. • Long test development time • Expensive ATE • Long test time. • Test stimuli: • Multiple types • Dependence wrt to the involved circuit • Test evaluation: • Multiple types (DC, AC, Transient, etc.) • Requires accurate and complex post-processing • Separate test for functionality and timing impossible.

14. uP Memory digital RF MixedSignal • Stimuli generation • Precision timing • Diagnostic • Test control • Power management • Large deep memory • Slow throughput • etc. Analogue and MS Test Current Status SUPER TESTER • Large Pin-Count • Large Data Volume • High Frequency Features • High Accuracy Features • etc

15. Analogue and MS TestAlternative Approach STRUCTURAL TEST Defect-Oriented Test There are no defects Stimuli Generator CUT ResponseInterpreter Defect Effects • The CUT structure must be known • Minimal test showing up defects • It takes shorter times • It requires simple instrumentation • Tests do not guarantee Specs

16. Analogue and MS Test Alternative Approaches Bothapproachesarecomplementary STRUCTURAL TEST FUNCTIONAL TEST Defect-Oriented Test There are no defects Specification-Based Test The Circuit Complies Specs Stimuli Generator CUT ResponseInterpreter Defect Effects I/O Behavior • The CUT is considered as a black box • All interesting I/O relationship must be checked out • Tests may overlap and be redundant • It takes long time • It requires different instrumentation • Tests do not guarantee defect-free ICs • The CUT structure must be known • Minimal test showing up defects • It takes shorter times • It requires simple instrumentation • Tests do not guarantee Specs

17. More to Test but Less Test Access uP Memory digital RF MixedSignal Fundamental problems with External Testing More Devices and less Pin/Device

18. More to Test but Less Test Access Yield Losses Source: SIA Roadmap ProjectedYield losses Device speed+30% per year Tester accuracy12% per year Fundamental problems with External Testing If current trends continue, in less than ten years, tester timing errors will approach the cycle time of the fastest devices.

19. Fundamental problems with External Testing • More to Test but Less Test Access • Yield Losses • ATE Cost Accuracy, Bandwidth, noise, pin-count, socket performance, memory, etc. accordingly to CUT. If current trends continue, it may cost more to test a transistor than to manufacture the transistor (by 2014).

20. SolutionsLines of interest • Standardized Test Access Mechanism • 1149.4 • P1500* • Structured Test planning • Enable hierarchical testing • Enable the re-use of on-chip resources (DSP, uP, etc.) • Facilitate parallel testing • etc. • Re-usable and structured DfT & BIST techniques • Provide accessing to embedded cores, • Reduce I/O data rate requirements, • Enable low pin count testing, and • Reduce the dependence on expensive instruments.

21. SolutionsStandard Test Access efforts • 1149.4 (started at the end of 1991) • Standard Mixed-Signal test bus to be used at device, sub-assembly and system levels. • Aims to increase the observability and controllability of Mixed-Signal designs and support MS-BIST structures. • P1500 (started in 1995) • Standard test method for embedded cores. • Focused on Standardized Core Test Language (CTL) and configurable & scalable test wrapper for easy test access to the core. • Need extension to mixed-signal.

22. SolutionsDfT & BIST • Re-usable and structured DfT & BIST techniques. • A DfT Technique is not a Test Technique. • An optimum strategy requires a synthesis of different DFT & BIST techniques. Layout Rules & guidelines General Support for specif. meas. Physical isolation & accessing Electrical Pre/Post processing tech. Block CircuitSpecific Partial / full BIST System On-line Test Hierarchy Techniques

23. SolutionsDfT & BIST • Re-usable and structured DfT & BIST techniques. • An optimum strategy requires a synthesis of different DFT & BIST techniques. Layout Optimization Layout Rules & guidelines Design for Iddq Support for specif. meas. Physical Sw-opamp Standard Test Bus (1149.4) isolation & accessing Electrical ADCBIST, PLLBIST MADBIST, HBIST On-Chip techniques Block Partial / full Self-Test Circuit Reconfiguration System Self-Checking archit. Concurrent Test Hierarchy On-Line Archit. Techniques Examples

24. SolutionsDfT & BIST • Re-usable and structured DfT & BIST techniques. Accessing Functional Layout Optimization Layout Rules & guidelines Design for Iddq Support for specif. meas. Physical Sw-opamp Standard Test Bus (1149.4) isolation & accessing Electrical ADCBIST, PLLBIST MADBIST, HBIST On-Chip techniques Block Partial / full Self-Test Circuit Reconfiguration System Self-Checking archit. Concurrent Test Hierarchy On-Line Archit. Techniques Structural Examples

25. MAIN ADVANTAGES Test the untestable: Embedded cores Measure functions faster than ATE IP protection Re-usability: Along IC life cycles: wafer, board, field Reduce ATE requirements Reduce test develop.&Applic. time REQUIREMENTS Put ATE functions into the chip: Test stimuli generation Output response analysis Test control Support for Board and System levels. Extra Area Design Efforts SolutionsBIST

26. SolutionsBIST • TECHNIQUES: • Functional:Meas Specs. Params • Structural: Signature analysis to detect faults and predict yield problems. EXAMPLES • HBIST [Ohletz91] • MADBIST[Toner&Roberts,93] • adcBIST [LogicVision] • PLLBIST [LogicVision] • adcBISTmaxx [Opmaxx] • OBIST (filters, ADCs, DACs, SD-mod, etc.) • Reconfiguration (filters, SD-mod, Pipeline ADCs, etc.) • Etc.

27. Available techniques Sinusoidal oscillators Relaxation oscillators Digital synthesizers SD–based Bit-streams generators White noise generators PWM generators Etc. Constrains Precission & Resolution Frequency range Multi-tone capability Linearity (ramps) Calibration Programmability Area Etc. SolutionsTest Stimuli Generators

28. DSP(FFT) AD AD Passband DIGITALFILTER Reject Band Signal Power Noise Power SolutionsOutput Response Analyzers Available techniques • Histograms • FFT • Bandpass digital filters • SD Signature analyzer • Sinewave correlation • Etc.

29. Reasons for DfT&BIST Portable: reusable along IC life cycle The only solution for embedded blocks Reduce cost of external ATE At-Speed Test Solves SOCs problems (accessing, IP protection) Simplifies Test Program Development External accessing to embedded blocks may impact performance Reasons for External ATE External ATE can do more testing BIST increase IC complexity BIST may impact performance BIST increase design efforts & time BIST may increase yield loss. Conclusions DfT&BIST vs External ATE

30. Conclusions • Further Research required:DfT & BIST techniques for analogue embedded cores • Many companies and researchers are providing since some years good solutions for a diversity of cores (PLLs, ADCs and DACs, filters, memories, etc.). • However, the industry has only adopted standards (1149.4) & functional solutions (adc-BIST, adcBISTmaxx, etc.) • Structural techniques not widely accepted, but they are a clear potential solution that need to be further explored.

31. On-ChipTest Manager • Stimuli generation • Result compression • Precision timing • Diagnostic • Power manager • Test Control • Support for board & system level ConclusionsDfT & BISTed ICs Low Bandwidth external interfaces NEED!!: Dedicate part of the IC area to include DfT and BIST facilities Memory (BISTed) External ATE Digital Tester Low cost-per-pin Limited speed Limited accuracy Logic (BISTed) Mixed-Signal (BISTed) I/O & Interconnects (BISTed) IC Ideal concept:DfT & BISTed IC High Bandwidth internal interfaces