NMOS-based high gain amplifier for MAPS

NMOS-based high gain amplifier for MAPS Andrei Dorokhov Institut Pluridisciplinaire Hubert Curien (IPHC) Strasbourg, France VI th INTERNATIONAL MEETING ON FRONT END ELECTRONICS FOR HIGH ENERGY, NUCLEAR, MEDICAL AND SPACE APPLICATIONS Perugia, Italy 17- 20 May 2006 e-mail address: Andrei.Dorokhov@IReS.in2p3.fr slides are available at http://www-lepsi.in2p3.fr/~dorokhov/talks/Andrei_Dorokhov_FEE2006.ppt

Contents • Amplifiers for MAPS – requirements, constraints and limitations • Introduction to an improved amplifier schematics • Implementation of the amplifier in test structures of Mimosa15 chip • Tests with Fe55 and results • Summary and future plans

Amplification is needed to decrease noise contribution from switching networks, like clamping or sampling. Amplifiers for MAPS • PMOS transistors not allowed inside pixel -> signal decrease due to parasitic NWELL • but using PMOS transistor as a load would be the preferred choice to increase in-pixel amplifier gain… load bias gate reset out bias in in out vb cascode signal current in

Amplifiers for MAPS small signal Gain = Vout/Vin = gm1 /(gm2 +gmb2 +gds1 +gds2) M2 bias As an example from simulation to be presented later: gm1=47 mS gm2=4 mS gmb2=0.9 mS gds1=8 nS gds2=0.5 mS out • gds1 and gds2 <<gm1,gm2 , gmb2 • so one need to increase gm1and decrease gm2 and gmb2 • with decreasing gm2 we decrease DC current, and hence gm1 so there is a limiting contradiction for the gain/bandwidth of this schematic… Id in M1 signal current Due to gm2 there is unwanted dependency of Id on Uout , so can we reduce dependency of Id on Uout without changing gm2 ? ?

-> decouple the gate of the load transistor from the power supply with one additional NMOS transistor, used as a diode Improved load for the common source transistor • due to the floating gate and parasitic gate-to-source capacitive coupling the AC voltage at the gate will follow to the output AC voltage -> • AC current and hence the load for the common source transistor decreases • load for DC is almost unchanged as DC voltage drop on additional NMOS transistor is small M3 M2 gate out bias in M1 signal current Gain = Vout/Vin = gm1 /(gm2 +gmb2 +gds1 +gds2) The AC gain should increase, while the DC operational point should not change!

New idea works - simulation with Spectre New schematic AC gain is 8dB larger! Standard schematic gmb2 +gds1 +gds2 become significant and limit the amplification, and also the gate is not perfectly decoupled -> still some fraction of gm2 exist…

Test structures with new amplifier implemented in Mimosa15 chip improved load with power on switch low frequency-pass feedback correlated double sampling circuit common source transistor with power on switch NWELL diode NWELL size is4.25 mm x 3.4 mm, pixel pitch size 30 mm x 30 mm, pixel matrix: 4 columns x 15 rows

5.9 keV gammas create about 1640 e-h pairs in silicon • pixel amplitude is determined as the voltage difference between two successive time frames (correlated double sampling) • the time between two successive frames is 500 ms (== integration time) • pixel readout time is 500 ns • measurements are performed at stabilized temperature of 20O • common mode and pedestals are subtracted Tests with Fe55 source, measurements Single pixel amplitudes distribution, superimposed for all 60 pixels, no amplitude cut is applied If gamma goes directly to the NWELL volume ( very small <<1% fraction of all gammas), all delivered charge will be collected by single pixel and this value used to determine conversion gain (mV/e) for the amplifiers

Tests with Fe55 source, calibration Each pixels is calibrated individually, example of calibration peak for pixel[0][7] • Events selection for the calibration peak amplitude distribution: • S/N (seed pixel) > 5 • S (seed pixel) > S (each of 8 pixels around seed pixel) • S/N < 10 for each of 8 pixels around seed • S/N < 5 for each of readout pixels in the ring 5x5 around 3x3

Tests with Fe55 source, calibration Distribution of calibration peaks for all pixels • Conversion gain is about 74 mV/e, including attenuation in source follower • Calibration peak variation is about 2 %, this includes charge-to-voltage conversion in NWELL diode, amplifier gain, source follower gain variations • Output voltage variation before CDS, due to process parameters variation (NWELL, amplifier transistors, source followers) is about 20 mV

Noise amplitude distribution for each pixel is fit to Gaussian, and sigma is taken as noise value for each pixel of 60 Tests with Fe55 source, noise Noise value distribution for all pixels, average noise is about 7.5 e or 540 mV at the column output

Tests with Fe55 source, charge collection Seed pixel amplitude distribution for all pixels, the most probable value for the collected charge in the seed pixel is about 300 e, or 18 % of total charge • Events selection for the seed pixel: • Border pixels are excluded • S/N (seed pixel) > 5 • S (seed pixel) > S (each of 8 pixels around seed pixel) • average {S (8 pixels around seed pixel)} > average {S (13 pixels around 3x3 cluster pixel)}

Tests with Fe55 source, charge collection in cluster of 3x3 Charge collection in 3x3 pixels cluster, the most probable value for the collected charge is about 950 e, or 58% of total charge Events selection: same as for the seed amplitude distribution

new resistive AC load, which uses only NMOS transistors, is proposed • NMOS based amplifier using new type of load and feedback is designed and simulated • the gain increases by factor of 2 in comparison to the gain of existing amplifier schematics, which use only NMOS transistors • in comparison to old schematic, the same gain can be achieved with smaller power consumption • the designed amplifier implemented in MAPS using AMS0.35 OPTO process and tested with Fe55 source • the tested MAPS has the following measured properties: • low noise, ~7.5 e (after CDS), and hence higher signal-to-noise ratio • conversion gain is about 74 mV/e • gain variation due to process variation is about 2 % • charge collection in seed pixel is 18 % • charge collection in the cluster 3x3 is 58 % • the amplifier can be also used in schematics, where one need to save the space, cause it does not contain PMOS transistors (and hence PWELLs) Summary

Future development plans • larger matrix and smaller pixel pitch size • amplifier optimization to use it in combination with clamping readout circuitry • 1 and 2 -> chip submission in June2006 in collaboration with DAPNIA/SEDI (CEA/Saclay) • test NMOS based high gain amplifier without feedback, different biasing -> more test structures…

Acknowledgements This development work would not be possible without support of many people from CMOS sensors group at IPHC: W. Dulinski and M. Winter – for encouraging me to improve the amplifier for MAPS and for the fruitful discussions, special thanks to W. Dulinski for making the layout for my four different amplifier designs of which actually only two worked (well…) CAD specialists - C. Colledani, F. Guilloux, S. Heini, A. Himmi, Ch. Hu, O. Robert, I. Valin, for their help with Cadence, Data acquisition, test and measurementsspecialists - G. Claus,M. Goffe, K. Jaaskelainen and M. Szelezniak for providing me test setup and acquisition software

NMOS-based high gain amplifier for MAPS