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彰師積體電路設計所 A 22Gb/s 6b DAC with Integrated Digital Ramp Generator ISSCC 2005 / SESSION 6 /HIGH-SPEED AND OVERSAMPLED DACs / 6.7. 指導教授 : 林志明 級別 : 碩一 學生 : 呂致遠. Outline. DA architecture Ramp generator architecture Experimental results using on-chip: ramp generator (test chip 1)
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彰師積體電路設計所A 22Gb/s 6b DAC with Integrated DigitalRamp GeneratorISSCC 2005 / SESSION 6 /HIGH-SPEED AND OVERSAMPLED DACs / 6.7 指導教授:林志明 級別:碩一 學生:呂致遠
Outline • DA architecture • Ramp generator architecture • Experimental results using on-chip: • ramp generator (test chip 1) • “sampling scope” (test chip 2) • memory/MUX (test chip 2) • Conclusion
Conclusion • SFDR • simplify testing • Applications • Direct Digital Synthesis for communication • radar systems • Arbitrary Waveform Generator 來源: http://64.233.167.104/search?q=cache:AvhWb77RugQJ:www.esmchina.com/ART_8800057698_617671.HTM.45797267+dac%E7%9A%84DNL&hl=zh-TW
References: • [1] T. Schaffer et al., “A 2 GHz 12-bit Digital-to-Analog Converter for Direct • Synthesis Applications,”GaAs IC Symposium, Tech. Dig. pp 61-64, 1996. • [2] A. Van den Bosch et al., “A 10-bit 1-GSample/s Nyquist Currrent- • Steering CMOS D/A Converter,”IEEE J. Solid-State Circuits, vol. 36, no. • 3, pp 315-324, March, 2001. • [3] B. Schafferer, R. Adams, “A 3V CMOS 400mW 14b 1.4GS/s DAC for • Multi-Carrier Applications,” ISSCC Dig. Tech. Papers, pp 360-361, Feb., • 2004. • [4] P. Vorenkamp et al., “A 1Gs/s, 10b Digital-to-Analog Converter,”ISSCC • Dig. Tech. Papers, pp 52-53, Feb., 1994. • [5] W. Cheng et al., “A 3b 40GS/s ADC-DAC in 0.12μm SiGe,”ISSCC Dig. • Tech. Papers, pp 262-263, Feb., 2004. • [6] A. Gutierrez-Aitken et al., “Ultrahigh-Speed Direct Digital Synthesizer • Using InP DHBT Technology,”IEEE J. Solid-State Circuits, vol. 37, no. 9, • p 1115-1119, Sept., 2002.