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Class 5 – Aol, Bandwidth, and Slew Rate. Nov 18, 2011. Open Loop Gain Aol. Remember from Class 2 – Close Loop Gain. Aol for different Amplifiers. Aol on OPA369. Let’s examine what happens to closed loop gains for variations of Aol. Note that Aol can be strongly effected by temperature.
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Class 5 – Aol, Bandwidth, and Slew Rate Nov 18, 2011
Open Loop Gain Aol
Aol on OPA369 Let’s examine what happens to closed loop gains for variations of Aol Note that Aol can be strongly effected by temperature
Closed Loop DC Gain Error(Error vs Gain Magnitude) Ideal Closed Loop Gain = 2 Avol = 120dB Ideal Closed Loop Gain = 101 Avol = 120dB
Closed Loop DC Gain Error(Error vs Gain Magnitude) Avol = 134dB, Gain = 101 Avol = 114dB, Gain = 101
Closed Loop DC Gain Error(Error vs Gain Magnitude) Avol = 134dB, Gain = 101 Avol = 90dB, Gain = 101 Over Temp!
Amplifiers where GBW is Different over Different Frequency ranges
Slew Rate
Remember from Class 1Constant Current -> Voltage Changes Linearly
Slew Limit • For slow moving or small signals iout < iout(max) • For large rapid moving signals iout = iout(max) • The output is slew rate limited • This is the fastest rate the output can change • The input is no longer a virtual short • Large input differential voltages are possible • Iout is constant so vout increases linearly across capacitor
Simulate Slew Rate OPA2188 Looking at the slope of the output signal. The rate of change is the slew rate.
Simulate Slew Rate OPA2188 The input no longer has the virtual short. The output changes cant keep up with the input.
Large Signal Step Response OPA827(Shows Slew Rate and Settling Time) SR = 10V / 0.4uS = 25V/uS (from graph) SR = 28V/uS (from data sheet table)
Slew Boost Slows down as Vout approaches Vin.
Current to Miller Capacitance IccWith and With out Slew Boost
Settling Time
Settling Time Slew Rate Note: Settling Time includes Slew Rate time
Simulating Settling Time Output Slew Output Settles Step input Settling time includes the slew and settling. We will zoom in on settling region. Step starts when step is applied at 1uS
Simulating Settling Time Use the post processor to set Limits Post processor Create limits for +/- 0.01% 9.999V and 10.001V
Simulating Settling Time 0.1% settling for a 10V signal 10V x 0.01% = 1mV |Output – 10V| < 1mV Data Sheet = 550nS Simulated = 400nS
Small Signal Step Response
Simulation Configuration Zoom in on rising Edge
Does a small signal Step put the device into slew limit? Rate of Change on Output Signal: ΔV/ Δt = 72.3mV / 6.17ns ΔV/ Δt = 11.7V/us From Data Sheet Slew Rate = 28V/uS This is what you would expect with a real device. A small signal step will NOT put the amplifier into slew limit.
The “Ringing” in small signal step response is related to stability Larger gain less overshoot gain=-1 is 2
Small Signal Step ResponseRise Time is independent of step size
Max Output vs. Freq Full Power BW
Maximum Output vs Frequencyalso called Full Power Bandwidth For Vs = +/-15V 10Vpk Distortion! 7.5Vpk No Distortion!