COMBINATIONAL LOGIC

1. COMBINATIONAL LOGIC

2. Overview

3. Combinational vs. Sequential Logic

4. At every point in time (except during the switching transients) each gate output is connected to either V or V via a low-resistive path. DD ss The outputs of the gates assumeat all timesthevalue of the Boolean function, implemented by the circuit (ignoring, once again, the transient effects during switching periods). This is in contrast to the dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high impedance circuit nodes. Static CMOS Circuit

5. Static CMOS

6. NMOS Transistors in Series/Parallel Connection • Transistors can be thought as a switch controlled by its gate signal • NMOS switch closes when switch control input is high A B NAND Gnd = Y = X if A and B X Y A NOR B Gnd = Y = X if A OR B X Y NMOS Transistors pass a “strong” 0 but a “weak” 1

7. PMOS Transistors in Series/Parallel Connection Vdd = NOR NAND Vdd =

8. Complementary CMOS Logic Style Construction (cont.)

9. Example Gate: NAND

10. Example Gate: NOR

11. Example Gate: COMPLEX CMOS GATE F = D(A+BC) F = D +A(B+C)

12. 4-input NAND Gate Vdd Out GND In1 In2 In3 In4

13. Properties of Complementary CMOS Gates

14. DC Characteristics of 2-Input NAND VOH = Vdd VOL = Gnd • VLT: Different based on Input • 11 – 01 • 11 – 10 • 11 -- 00 Va 11 – 01: Similar to Inverter with resistor in source circuit 11 – 10: Similar to Inverter with resistor in drain circuit 11 – 00: Similar to Inverter with b’p = 2bp & b’n = 1/2bn Vb

15. DC Characteristics of 2-Input NAND Vgs1 = VLT; Vgs2 = VLT – Vds1; VLT = Vds1 + Vds2 Vgs2 = Vds2  M2 is saturated  M1 is linear Id; VLT M2 VLT M1 Parallel Combination:

16. DC Characteristics of 2-Input NAND • In design: • Set one (middle) VLT = Vdd/2 • Distribute about Vdd/2 • Make mean = Vdd/2

17. Transistor Sizing

18. Propagation Delay Analysis - The Switch Model

19. What is the Value of Ron?

20. Numerical Examples of Resistances for 1.2mmCMOS

21. Analysis of Propagation Delay

22. Design for Worst Case

23. Influence of Fan-In and Fan-Out on Delay

24. tp as a function of Fan-In

25. Fast Complex Gate - Design Techniques

26. Fast Complex Gate - Design Techniques (2)

27. Fast Complex Gate - Design Techniques (3)

28. Fast Complex Gate - Design Techniques (4)

29. Example: Full Adder

30. A Revised Adder Circuit

31. Ratioed Logic

32. Ratioed Logic

33. Active Loads

34. Load Lines of Ratioed Gates

35. Pseudo-NMOS

36. Pseudo-NMOS NAND Gate VDD GND

37. Improved Loads • M2 is long (large resistance) • M1 is enabled when A, B, C and D have been asserted. • Fast Pull-Up • Low VOL • More power consumption

38. Improved Loads (2) V V DD DD • Only useful if Out & Out are needed. M1 M2 Out Out A A PDN1(F) PDN2 (not F) B B V V SS SS Complementary Dual (differential) Cascode Voltage Switch Logic (DCVSL)

39. Example

40. Pass-Transistor Logic B Out A Switch s t Out u p n Network B I B • N transistors (small) • No static consumption

41. C = 5 V Vg= 5 V M 2 A = 5 V B Vd = 5 V M n Vs M C 1 L does not pull up to 5V, but 5V - V B Threshold voltage loss causes static power consumption NMOS-only switch (Passing a “1”) [Vtn(Vsb) > |Vtp|]  M2 is ON V TN

42. C = 5 V Vg= 5 V M 2 A = 5 V B Vs = 0 V M n Vd M C 1 L does pull up to 0V V B No threshold voltage loss causes No static power consumption NMOS-only switch (Passing a “0”)

43. C = 5 V Vg= 5 V M 2 A = 5 V B Vs = 0 V M n Vd M C 1 L NMOS-only switch (Transient Response)

44. Transmission Gate • Parallel combination of NMOS and PMOS • Full signal swing since: • NFET  “0” well • PFET  “1” well • Improved speed (parallel resistors) • Larger & requires inverter

45. 30000.0 (W/L) =(W/L) = p n 1.8/1.2 20000.0 ) m h O ( R 10000.0 0.0 0.0 1.0 2.0 3.0 4.0 5.0 Vout Resistance of Transmission Gate R n For Tgate passing a “1” R p R eq

46. S S Pass-Transistor Based Multiplexer S VDD GND In1 In2 S

47. Transmission Gate XOR

48. Delay in Transmission Gate Networks

49. Elmore Delay (Chapter 8)

50. Delay Optimization Mopt ~ 3 - 4