Network On Chip Platform

1. Instructor: Yaniv Ben-Itzhak Students: Ofir Shimon Guy Assedou Network On Chip Platform FINAL PRESENTATION - SPRING 2009 - Spring 2009

2. General Concept • NoC - Network On Chip A network-like structure composed of inter-connected modules which exchange data efficiently and in very fast rates Spring 2009

3. NoC Platform –Project Definition • Design and build basic NoC CPU Module as a part of multi-core NoC platform on an FPGA, and implement a tailored HW/SW verification system. Spring 2009

4. NOC Platform Architecture NIOS II softcore NIOS II softcore ADAPTOR (cpu-router) ADAPTOR (cpu-router) ROUTER ROUTER ROUTER ROUTER ROUTER ADAPTOR (router-memory) ADAPTOR (cpu-router) ADAPTOR (cpu-router) NIOS II softcore NIOS II softcore MEMORY CONTROLLER Spring 2009

5. CPU Module Architecture NIOS II softcore NIOS II softcore NIOS II softcore System Interconnect Fabric (BUS) ADAPTOR (cpu-router) ADAPTOR (cpu-router) ROUTER ROUTER CPU-ROUTER ADAPTOR ROUTER packets ROUTER ROUTER ROUTER ADAPTOR (cpu-router) ADAPTOR (cpu-router) ADAPTOR controls NIOS II softcore NIOS II softcore MEMORY CONTROLLER Avalon MM Interface Spring 2009

6. System Configuration • Nios II soft-core • CPU freq – 100 MHz • Pipeline • Increase throughput for peripherals that require several cycles to return data • Two phase pipeline – Address & Data • Only Read requests can be pipelined • System Interconnect Fabric • Selected Bus Interface - Avalon Memory Mapped: Used for R/W interfaces on master and slave components in a memory-mapped system Spring 2009

7. System Configuration • Router • Virtual channels - One channel was defined for both R/W operations in order to keep static routing in the platform. • Flit type - Head & tail - easy to implement • System • Clock frequency – 100 MHz • Max Packets per CPU Module – 16 • Packet size – 77 bits Spring 2009

8. Packet Packet Structure Packet Header Flit Service Level Packet Type Flit Header Data Service Level 76 Packet Type 75 74 Processor ID 73 72 Request Type 71 Data 70 39 38 8 Address Memory X Coordinate 7 4 Memory Y Coordinate 3 0 Spring 2009

9. Adaptor Architecture NIOS II softcore System Interconnect Fabric (BUS) address flit BUFFER IN (FIFO) packet data control control ROUTER CPU-ROUTER ADAPTOR packets ROUTER_TX waitrequest CREDITS CALCULATOR control control data packet controls BUS_TX Avalon MM Interface control control Spring 2009

10. Verification & Validation • Behavioral Simulations • Pre-synthesis VHDL for logic functionality with ModelSim • Develop Verification Environment • Full System Testing • Create high load of memory accesses in system Spring 2009

11. Verification System Architecture TESTER System Interconnect Fabric (BUS) NIOS II softcore CPU Module LOOPER packets ROUTER CPU-ROUTER ADAPTOR packets controls controls Avalon MM Interface Spring 2009

12. Screen clipping taken: 29/06/2009, 12:22 Behavioral Simulations -Write Waveforms Spring 2009

13. Screen clipping taken: 29/06/2009, 12:22 Behavioral Simulations -Read Waveforms Spring 2009

14. LOOPER Module Architecture TESTER System Interconnect Fabric (BUS) Nios II CPU Module BUFFER IN (FIFO) LOOPER packet packet packet control ROUTER CPU-ROUTER ADAPTOR packets CREDITS CALCULATOR ROUTER_TX controls control packet control control Spring 2009

15. Verification Software • Harsh and intensive environment that will test the hardware • Write/Read randomly to memory • Increased paced in compare to average memory access rate Spring 2009

16. Verification Software - Pseudo-Code Spring 2009

17. Test Results • Program Iteration Example: • Final Results: Spring 2009

18. FPGA Resources Usage Spring 2009

19. Development Tools • Hardware: • GIDEL ProcStar II 180 Board • Stratix II 60 FPGA • PC • Software: • Quartus II • SOPC Builder • NIOS II IDE • ModelSim • GIDEL PROCWizard Spring 2009

20. Project Milestones Spring 2009

21. Achievements & Further Work • Main Project Achievements • Fully operational NOC based system in hardware (FPGA) • Modular CPU Module - building block which enables easy scalability of future NOC platforms • Verification & Validation environment (HW & SW) • Further Work • Complete Memory Module Implementation • Complete Platform integration • In-depth Platform analysis Spring 2009

22. Thank you! Spring 2009

23. Adaptor interconnections • Router • Virtual channels • can be modified as required. • 2 channels were defined. One for Read requests and one for Write requests. • Flit type • Three types – head, tail & head and tail • Only head & tail - easy to implement NIOS II softcore System Interconnect Fabric (BUS) ROUTER CPU-ROUTER ADAPTOR packets controls Avalon MM Interface Spring 2008

24. Adaptor interconnections • System Interconnect Fabric - Bus • Available interfaces to SIF • Clock Interface • Interrupt Interface • Avalon Memory-Mapped Tristate Interface • Avalon Streaming Interface • Conduit Interface • Avalon Memory-Mapped Interfaces • Interface to Bus is Avalon Memory Mapped • Used for R/W interfaces on master and slave components in a memory-mapped system NIOS II softcore System Interconnect Fabric (BUS) ROUTER CPU-ROUTER ADAPTOR packets controls Avalon MM Interface Spring 2008

25. Adaptor interconnections • Slave Transfers: • Typical Slave Read and Write Transfer • Burst Transfer • Pipelined Transfer • Pipeline • Increase throughput for peripherals that require several cycles to return data • Two phase pipeline – Address & Data • Only Read requests can be pipelined NIOS II softcore System Interconnect Fabric (BUS) ROUTER CPU-ROUTER ADAPTOR packets controls Avalon MM Interface Spring 2008

26. Nios II Sofcore Processor Spring 2009