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Chapter 3.2 : Virtual Memory

Chapter 3.2 : Virtual Memory. What is virtual memory? Virtual memory management schemes Paging Segmentation Segmentation with paging Page table management. Problems with Memory Management Techniques so far. Unused (wasted) memory due to fragmentation

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Chapter 3.2 : Virtual Memory

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  1. Chapter 3.2 : Virtual Memory • What is virtual memory? • Virtual memory management schemes • Paging • Segmentation • Segmentation with paging • Page table management

  2. Problems with Memory Management Techniques so far • Unused (wasted) memory due to fragmentation • Memory may contain parts of program which are not used during a run (ie., some routines may not be accessed in that particular run) • Process size is limited with the size of physical memory • Process needs contiguous space in real memory for execution

  3. Virtual Memory (VM) Virtual memory of process on disk Map (translate) virtual address to real Real memory of system

  4. Virtual Memory (VM) • VM is conceptual • It is constructed on disk • Size of VM is not limited (usually larger than real memory) • All process addresses refer to the VM image • When the process executes all VM addresses are mapped on to real memory

  5. Did We Solve the “Problems”? 1. Unused (wasted) memory due to fragmentation (We’ll see!) 2. Memory may contain parts of program which are not used during a run • YES! Virtual memory contents are loaded into memory on demand 3. Process size is limited with the size of physical memory • YES! Process size can be larger than real memory

  6. Page # Offset within page (Pure) Paging • Virtual and real memory are divided into fixed sized pages • Programs are divided into pages • A process address (both in virtual & real memory) has two components

  7. Interpretation of an Address • 16 bits for addressing means that the memory addressed is 64K bytes (0000 -FFFF) • Suppose page size is 4K bytes (12 bits) • The virtual memory has 16 pages (4 bits) • Real memory can have at the most 16 pages • Example : address : 7 F B C 0111 1111 1011 1100 Page # Offset

  8. The relation betweenvirtualaddressesand physical memory addresses 64K Virtual Memory 32K Real Memory

  9. Paging (Cont.) • When process pages are transferred from VM to real memory, page numbers must be mapped from virtual to real memory addresses • This mapping is done by software & hardware • When the process is started only the first page (main) is loaded. Other pages are loaded on demand

  10. Virtual Memory – Memory Management Unit The position and function of the MMU

  11. Note that virtual address is 16 bits (64K virtual memory) but the physical address is 15 bits (32K real memory) Internal operation of MMU with 16 4 KB pages

  12. Page Table Entry Page Table 0 Page frame # 1 2 3 Page protection 4 5 Reference bit 6 Modification bit 7 8 Validity bit Page Tables • Index of page table is the virtual page #

  13. Page Table Entry Fields • Validity bit is set when the page is in memory • Reference bit is set set by the hardware whenever the page is referred • Modified bit is set whenever the page is modified • Page-protection bits set the access rights (eg., read, write restrictions)

  14. Virtual memory address Page Table Register + PT 1 Catenate PT2 . . Page # Offset within page PTn Page tables of processes Address Mapping in Paging Real memory address

  15. Address Mapping in Paging (Cont.) • During the execution every page reference is checked against the page map table entry • If the validity bit is set (ie., page is in memory) execution continues • If the page is not in memory a page fault (interrupt - trap) occurs and the page is fetched into memory • If the memory is full, pages are written back using a page replacement algorithm

  16. Memory Management Problems : Re-visit due to paging 1. Unused (wasted) memory due to fragmentation • ONLY on the last page (Page Break) 2. Memory may contain parts of program which are not used during a run • Virtual memory contents are loaded into memory on demand 3. Process size is limited with the size of physical memory • Process size can be larger than real memory • Furthermore, program does not occupy contiguous locations in memory (virtual pages are scattered in real memory)

  17. Segmentation • Pages are fixed in size, segments are variable sized • A segment can be a logical entity such as • Main program • Some routines • Data of program • File • Stack

  18. Segment # Offset within segment Segmentation (Cont.) • Process addresses are now in the form • Segment Map Table has one entry for each segment and each entry consist of • Segment number • Physical segment starting address • Segment length

  19. Segmentation (1) • One-dimensional address space with growing tables • One table may bump into another

  20. Segmentation (2) Allows each table to grow or shrink, independently

  21. Segmentation (3) Comparison of paging and segmentation

  22. Implementation of Pure Segmentation (a)-(d) Development of fragmentation (e) Removal of the fragmentation by compaction

  23. Problems with Segmentation • Similar problems in dynamic partitioning • Fragmentation in real memory • Relocation is necessary for compaction

  24. Segment # Page # Offset within page Segmentation with Paging • Segmentation in virtual memory, paging in real memory • A segment is composed of pages • An address has three components • The real memory contains only the demanded pages of a segment, not the full segment

  25. Segment # Page # Offset within page Addressing in Segmentation with Paging Segment Table Page Tables Pages

  26. How Big is a Page Table? • Consider a full 2 32 byte (4GB) address space • Assume 4096 byte (2 12 byte) pages • 4 bytes per page table entry • The page table has 2 32/2 12 (= 2 20 ) entries (one for each page) • Page table size would be 2 22 bytes (or 4 megabytes)

  27. Problems with Direct Mapping? • Although a page table is of variable length depending on the size of process, we can not keep them in registers • Page table must be in memory for fast access • Since a page table can be very large (4MB), page tables are stored in virtual memory and be subjected to paging like process pages

  28. How to Solve? • Two-level Lookup • Inverted Page Tables • Translation Lookaside Buffers

  29. Directory Page Offset Virtual Address - 32 bits (4 GB) 12 bits - 4096 Byte pages 10 bits - 1024 pages 10 bits - 1024 directories Two-Level Lookup

  30. Dir Page Offset + + Page Table Physical Address Page Directory Two-Level Lookup (Cont.)

  31. Two-Level Lookup (Cont.) • A process is represented by one or more entries of the page directory (ie., several page tables) • Typically a page table size is set as one page which makes swapping easier • This is one of the addressing schemes used by Intel family of chips (Intel chips can use paging, segmentation or a combination of both)

  32. Virtual Address hash Hash Table Page # Offset within page Inverted Page Tables Page # PID 21 17 76 23 Page # 101 Process # 17 Hash # 2 3 213 32 Page Frame Table

  33. Inverted Page Tables (Cont.) • The virtual page number is hashed to point to a hash table • The hash table contains a pointer to the inverted page table • Inverted page table contains page table entries (one for each real memory page) • Entries having the same hash codes are chained

  34. Inverted Page Tables (Cont.) • A fixed portion of memory is used for mapping regardless of the number of processes or virtual pages • This approach is used by IBM’s AS/400 and RISC System/6000 computers

  35. Virtual Address Page # Offset TLB TLB Hit Page Table TLB Miss Frame # Offset Real Address Page Fault Translation Lookaside Buffer

  36. Translation Lookaside Buffer (Cont.) • Translation lookaside buffer (TLB) is a cache for page table entries • TLB contains page table entries that have been most recently used • Whenever the page table is referred (TLB miss), the page table entry is also copied to the TLB • TLB is usually an associative memory (content addressable memory)

  37. TLBs – Translation Lookaside Buffers A TLB to speed up paging

  38. Segmentation with Paging: MULTICS (1) • Descriptor segment points to page tables • Segment descriptor – numbers are field lengths

  39. Segmentation with Paging: MULTICS (2) A 34-bit MULTICS virtual address

  40. Segmentation with Paging: MULTICS (3) Conversion of a 2-part MULTICS address into a main memory address

  41. Segmentation with Paging: MULTICS (4) • Simplified version of the MULTICS TLB • Existence of 2 page sizes makes actual TLB more complicated

  42. Segmentation with Paging: Pentium (1) A Pentium selector

  43. Segmentation with Paging: Pentium (2) • Pentium code segment descriptor • Data segments differ slightly

  44. Segmentation with Paging: Pentium (3) Conversion of a (selector, offset) pair to a linear address

  45. Segmentation with Paging: Pentium (4) Mapping of a linear address onto a physical address

  46. Segmentation with Paging: Pentium (5) Protection on the Pentium Level

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