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7-things that we should know about Op-amp Design

7-things that we should know about Op-amp Design. Natsem India Design’s Pvt. Ltd. 7-things that we should know about Op-amp Design. T. Srinivas. Staff Engineer Data Converters Group. 2. Fear of Op-amp. In Analog Circuit Design Course. Design Systems. Objective.

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7-things that we should know about Op-amp Design

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  1. 7-things that we should know about Op-amp Design Natsem India Design’s Pvt. Ltd.

  2. 7-things that we should know about Op-amp Design T. Srinivas Staff Engineer Data Converters Group. 2

  3. Fear of Op-amp In Analog Circuit Design Course Design Systems Objective • Op-amp is a fundamental part of Analog Circuit Design. • Our aim is to increase your familiarity with Op-amp Design and…

  4. Contents

  5. Triode Region: D G Saturation Region: S VGS3=VGS2+0.1 VGS2=VGS1+0.1 VGS1 1. Small Signal Model of MOSFET.

  6. 1. Small Signal Model of MOSFET. Regions of Operation

  7. Triode Region: D G Saturation Region: S D VGS=VDC+Vin G Vin VDC S 1. Small Signal Model of MOSFET. • For Designing Amplifiers, MOSFET Operating in Saturation Region is preferred [IDS depends on Input!]. • To achieve -100dB THD Vin < (VGS- VTH)*40mV. • The small signal model that we show is valid for MOSFET in Saturation Region and for Vin<< VDSAT.

  8. VDD R VDS = VDD – IDS*R VDS = VDD – IDS*R – Iin*R D G VDC S VDC + vin vout= - gm*vin*R Eff D G vin R rds gm*Vin CGS S 1. Small Signal Model of MOSFET. • This signal model is sufficient for first-cut hand calculations.

  9. Intrinsic Gain D G vout= - gm*vin*rDS D G S vin rDs gm*Vin S 1. Small Signal Model of MOSFET. • To Increase Gain reduce VDSAT or increase length of MOSFET.

  10. Intrinsic Bandwidth Iout D G Iin vin rDs CGS gm*Vin S Gain-Speed Product = 1. Small Signal Model of MOSFET. • To Increase Bandwidth increase VDSAT or decrease the length of MOSFET.

  11. 1. Small Signal Model of MOSFET. L=0.5um L=1.5um L=1.0um L=1.0um L=1.5um L=0.5um L=0.5um L=1.0um L=1.5um

  12. Example 1: VDD gm2*0 rDS2 M2 G VOUT vin gm1*Vin rDS1 Vin VDC M1 S DC Gain AC Gain 1. Small Signal Model of MOSFET.

  13. These are the Basic Building Blocks of Analog IC design. Not Again. It doesn’t make any sense. VDD VDD 10uA 10uA gDS1=1e-6 S & gDS2=0; VOUT 10uA 0uA VOUT 1V 9uA 1uA M2 M1 M2 M1 1V 0V 10uA 0uA 2. Current Mirrors. Let (W/L)1=(W/L)2 VT=0.8V, gDS=0 VOUT = 0.0V IDS2 = 0 VOUT = 0.1V IDS2 = 7.5uA VOUT = 0.2V IDS2 = 10uA VOUT = 1.0V IDS2 = 10uA VOUT = 0.2V IDS2 = 9uA VOUT = 0.1V IDS2 = 6.75uA VOUT = 0.0V IDS2 = 0 VOUT = 1.0V IDS2 = 9uA Let (W/L)2=2*(W/L)1 VOUT = 1.0V IDS2 = 20uA If gDS1 = gDS2 =1e-6; IOUT=10uA VOUT= ??? VOUT=2V IOUT=???

  14. Small Signal Analysis VOUT G VDD vin gm1*Vin gm1*Vin gm2*Vin gm2*Vin rIN rDS1 rOUT rDS2 10uA VOUT S rIN rOUT M2 M1 VOUT G CGS1 CGS2 vin rDS1 rDS2 S 2. Current Mirrors. = 0 Due to CGS we have a Pole Here

  15. Better Current Mirror à Large Output resistance. VDD VDD I1 I1 VOUT VOUT V2 V2 V1=VGS3 V2=VGS5 V3=V2 – VGS4 > VDSAT M4 M2 M5 M2 M4 V1 V3 V3 V1 V1 V1=VGS3 V2=VGS3 + VGS4 M3 M1 M3 M1 • M1 – M3 is the Current Mirror. • M4 – M2 helps in achieving high resistance. • VOUT > V3 + VDSAT2 > 2*VDSAT • M1 – M3 is the Current Mirror. • M4 – M2 helps in achieving high resistance. • Requires high turn on voltage. VOUT > V1+VDSAT2 2. Current Mirrors.

  16. Wide Swing Current Mirror. VDD I1 I1 VOUT V2 M5 M2 M4 V3 V3 V1 M3 M1 If M1 – M4 are of same size, for a = 1.25, (W/L)5 = 1/5 (W/L). W/L W/L W/L 1/5 (W/L) W/L W/L 2. Current Mirrors. • There are Two Questions that we should answer. • How should we generate V2. • We know V3 = a VDSAT, what is the exact value of ‘a’. a = 1.5 is fine

  17. Example 2: VDD VDD VDD M3 M2 R M2 VOUT VOUT Vin VOUT Vin VDC M1 Vin M1 • If gm=100*gDS Gain = 50. • Gain varies with Process. • If (W/L)2=(W/L)1 Gain = 3. • Gain varies with Process. 2. Current Mirrors. • Replace the R with MOSFET and Build an • Amplifier with Gain = 50 • Amplifier with Gain of 3 (Kn=3*Kp).

  18. Example 3: VDD 10uA 150uA M2 (W/L)=2 M4 (W/L)=1 M1 (W/L)=??? 20uA M3 (W/L)=1 2. Current Mirrors. (a) (b) VDD M2 2*(W/L) MB1 (W/L) VOUT = ? 10uA M1 (W/L) MB1 (W/L) VGS4 + VGS3 = VGS2 + VGS1 (W/L)1 = 15. The above loop formed by Gate-Source voltages is known as Trans-linear loop. VOUT will near to VDD M2 in Triode region M1 in Saturation Region

  19. R VOUT VIN C 3. Gain Bandwidth Product of an Op-amp. 1st order Low Pass Filter mag(VOUT) Phase (VOUT) VIN VOUT

  20. VIN VOUT + - 3. Gain Bandwidth Product of an Op-amp. Op-amp in Feed-back. • Amplifier GBW required to settle in the given time (Ts) and with in given error (e).

  21. VIN VOUT + - 3. Gain Bandwidth Product of an Op-amp. Example 4: • Design a Amplifier with Gain of 4, operating at 100MHz and it should settle with 10-bit accuracy for a full-scale output of 1V.

  22. I Designed an Oscillator. Phase Margin is not enough. Poles are not in the right location. Lets Change some W/L’s and see. VOUT VIN = 1V 4. Stability of an Op-amp. • We use simple design technique to deal with stability issues. • This approach is sufficient to deal with most of the circuits and systems.

  23. Two-Stage Amplifier sCC VOUT v1 vIN Poles VDD M3 M4 sC1 sCL gmi. vIN gdsi gmo. v1 gdso DV DV*gm5 M5 DVOUT M2 M1 VOUT CC CL I1 I2 4. Stability of an Op-amp. DVOUT=0 VN VP

  24. Two-Stage Amplifier b VN VOUT VIN VP 4. Stability of an Op-amp. Op-amp in Feedback should be stable.

  25. Two-Stage Amplifier- Condition for Maximally flat response. b • To satisfy Assumption, We use the following rule of thumb. VN VOUT VIN VP 4. Stability of an Op-amp. Equate it to 2nd order Butterworth equation.

  26. Example 5: VN VOUT VIN VP b 4. Stability of an Op-amp. • Design a Amplifier with Gain of 2, operating at 1MHz and when 1V input is applied output should settle with in 2V ± 2mV. [A0=1e7]

  27. VDD = 5V M3 M4 M5 VOUT M2 M1 CC CL I1 I2 3V Linear system 2V Slew-rate limited 4V 4V 3.8 2V 3V 3V 1V 2V 2V 3V 5. Slewrate of an Op-amp. VOUT = 3V VOUT = 2V VIN = 2V VIN = 3V 3V 2V A Slew-rate limited system will cause non-linearity.

  28. Output Stage can supply huge current VIN = 2V Output Stage current limited 5. Slewrate of an Op-amp. f1 f2 f1 VOUT f2 VIN = 2V • Often in switched capacitor circuits, output stage current limitation leads to op-amp slewing. • In continuous time circuits where we have to drive resistor loads, output stage current limitation leads to non-linearity.

  29. VDD = 5V • Two-stage op-amp with class-AB output stage I2 I2 M11 M3 M4 CC M5 VOUT VN VP M6 CC M2 M1 CL M8 M12 M7 I1 M9 M10 5. Slewrate of an Op-amp. • Class-AB output stage should be used when driving resistor loads and some switched capacitor circuits. • Class-AB input stage can be employed to reduce power.

  30. 5. Slewrate of an Op-amp. Design Considerations for Slewrate (Switched capacitor Circuits). TSlew TSettle TCLK/2 TCLK

  31. Example 6: VDD = 5V I2 I2 f1 f1 f2 M3 M4 CS VIN CF f2 f1 f2 M2 M1 VOUT M5 M6 I1 f1 CL M7 M8 5. Slewrate of an Op-amp. 2.5V • Design a Amplifier with Gain of 2 for 10-bit ADC, operating at clock frequency of 1MHz with a Maximum input amplitude of 1V. Assume CF=1pF and CL=1pF.

  32. Example 6: vOUT CF v1 CP CS gDS gm*v1 CL vIN 5. Slewrate of an Op-amp.

  33. Example 6: What is this 5. Slewrate of an Op-amp.

  34. Example 6: Op-amp Can’t supply Infinite current. vOUT CF v1 CP CS gDS gm*v1 CL vIN 5. Slewrate of an Op-amp.

  35. Example 7: 5. Slewrate of an Op-amp. • Below op-amp should be designed for a Slewrate of 6V/us, what should be the input stage tail current if the op-amp is folded cascode op-amp. • ‘VIP, VIN’ forms fully differential signals (2VPP) with ‘VCM’ as common mode. 10pF VIP 1pF Parasitic Caps. VCM=1V 1pF VIN 10pF • Minimum Tail Current = 12uA.

  36. VDD = 5V 15u/1.5u M3 M4 M5 5.3u/1.5u VOUT M2 M1 CC CL 6. Offset of an Op-amp. 1. Systematic Offset: Case 1: VDSAT and Length of M3-M4 & M5 are same. Offset=48uV Case 2: VDSAT of M3-M4 & M5 is same but Length is different Offset=715uV Case 3: Length of M3-M4 & M5 is same but VDSAT is different Offset=718uV 10uA 10uA 10*15u/1.5u 40*15u/1.5u 10*5u/0.5u 2.5V 20uA 100uA

  37. VDD = 5V V4 M3 M4 V5 M5 V2 VOUT M2 M1 CC 20uA V7 M6 M7 6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations • Process steps like Photolithography, Etching and Deposition are not uniform. • Values of V1,V2, V3 depends on the sigma of the process. Normally they will be in the order of ‘mV’. • Proper layout [Common-Centroid Layout, proximity matching] techniques can reduce the mismatch, thus Offset. • Can a designer play a role in reducing the over-all Offset. 100uA

  38. VDD = 5V M3 M4 M5 VOUT V5=(gm7*V7/gm5) M2 M1 CC 20uA V7 M6 M7 6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations Input Referred Offset Due to: VB2 & V5 VIN VIN + V5/A1 100uA + gm7*V7 100uA

  39. 10uA + gm4*V4 6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations Input Referred Offset Due to: V2 & V4 VDD = 5V V4 M3 M4 M5 VOUT VIN M2 M1 VIN+(gm4/gm2)*V4 CC 20uA M6 M7

  40. 6. Offset of an Op-amp. 2. Random Offset : Due to Process Variations • Design M1-M2 (Differential Pair) and M3-M4 (Current Mirror) Carefully. • Decrease gm4 (For given ‘I’ Increase VDSAT for Current Mirrors). • Increase gm2 (For given ‘I’ Decrease VDSAT for Differential pair). • To reduce V2 and V4, use Large devices (Large L and Large W). Mismatch is inversely proportional to the Area of the MOSFET.

  41. 7. Noise of an Op-amp. Types of “Noise” • Interference • Cross talk, Clock Coupling… • Supply Noise. • Taken Care by proper design (Shielding, Differential circuits, etc…) • Device Noise • Thermal Noise (Fundamental). • Process related (1/f noise).

  42. 7. Noise of an Op-amp. Thermal Noise: • Dissipative elements (resistors, MOSFET’s, …) • Random fluctuations of v(t) of i(t). • White noise with zero mean. Resistor MOS Noise (Strong inversion) R *

  43. Case 1: Case 2: R * 100nF 100nF 1K 100K C C Total Noise=200nV 100K 1K 7. Noise of an Op-amp. kT/C Noise (Resistor): R

  44. VDD = 5V M3 M4 in32 in42 M5 VN in12 in22 M2 VOUT VP M1 CC MB1 MB2 vn2 7. Noise of an Op-amp. Noise Analysis is Similar to offset Analysis We can neglect the noise due to M5 & MBX. Assume gm1=gm2 & gm3=gm4 Calculating the input referred noise. kT/C Noise (Op-amp):

  45. For b=1, CC=10pF and gm1=gm3=80uS Noise at the output VoutRMS=32uV. 1/f - noise is suppressed by assigning kf=0 b Vout A(s) Total Noise=40uV vn2 Output Noise 7. Noise of an Op-amp. kT/C Noise (Op-amp): • Caution: RHS Zero is neglect for calculations, for a poor design it will increase the total output - noise drastically.

  46. 7. Noise of an Op-amp. 1/f Noise (‘Fake’ Noise): • Caused by traps in semiconductor material • Due to contamination or crystal defects • Has a 1/f power spectral density • Figure of Merit is called ‘Kf’ and Kf=A/ToxB. • Kf is process dependent. • For TOX>900A, NMOS(Kf) > PMOS(Kf). So PMOS is less noisy.

  47. Kf=1.36e-27, IDS=500uA flo=1Hz, fhi=1MHz, Tox=1250A W/L=140u/1u 1V 1V W/L IRMS=40nA 7. Noise of an Op-amp. 1/f Noise (‘Fake’ Noise): W/L=140u/1u W/L=35u/1u W/L=70u/2u

  48. CONCLUSION • I hope the topics covered would be useful as a starting point and help you to extend the concepts to system level issues. • I express my gratitude to following people: • Inventors of Google. • My Professors at IIT Madras. • For Natsem India and RVCE. • For SANYO Japan.

  49. About Author Area of Interest:Analog/Mixed-signal Integrated Circuit Design, with focus on SD Data converters. Education:M.Tech, Microelectronics and VLSI Design, IIT Madras, Chennai, 2001.B.Tech, Electronics & Communications, S.V University, Tirupati, 1999. Work Experience Associated with SANYO LSI, India (Feb ‘01 - April ‘05). Associated with Natsem, India (May ‘05 - Present). Design Experience:Multi-stage rail-to-rail operational amplifiers, Switched capacitor Circuits.Architectures for 20-bit/24-bit ADC/DAC.

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