Dr. Li-Rong Zheng ( 郑立荣 博士) Laboratory of Electronics and Computer Systems

1. Presentation to Taiwan SoC Consortium Visitors(2002-06-06, Kista-Stockholm)SoC Education and Interconnect-Centric SoC Design at KTH Dr. Li-Rong Zheng (郑立荣 博士) Laboratory of Electronics and Computer Systems Royal Institute of Technology (KTH) SE-164 40 Kista-Stockholm Sweden E-mail: lrzheng@imit.kth.se URL: http://www.imit.kth.se/~lrzheng

2. KISTA SCIENCE PARK is number two in the world • In July 2000 Wired Magazine presented its latest ranking concerning global science parks which placed Kista Science Park on second place together with Boston and Israel. Kista Science Park is a strong contender for the title of being the European version of Silicon Valley. • Cross fertilization between companies, research & development and schools of higher education continually generate new ideas. This is the driving force of increasingly rapid development of IT companies within KISTA SCIENCE PARK. KISTA SCIENCE PARK is situated in northwestern Stockholm. Today KISTA SCIENCE PARK nourishes some 700 companies, 28 000 employeés and 3 300 students at university level.

3. The IT University in Kista - A "virtual" university The IT University is the common name for all academic activities in Kista / Stockholm. It is a joint venture between KTH (the Royal Institute for Technology) and Stockholm University as partners. Karolinska Institutet (the medical university) becomes partner in the venture from fall 2001. Central Function: Vice-President for Academic Affairs Prof. Gunnar LandgrenDean Prof. Hannu TenhunenVice-Dean Prof. Björn Pehrson Departments Department of Microelectronics and Information Technology (IMIT) Department for System and Computer Science (DSV) Department of Applied Information Technology Centers KTH Online KTH Semiconductor Laboratory (Central Clean Room) Swedish Center for Internet Technology KTH Center for Wireless Systems Figures from 1999. (Aprox.) Undergraduate fulltime: 2 500 Students total 3 500 Researchers: 140 No. of employees 440 Turnover MSEK 400

4. Campus Kista Electrum: Isafjordsgatan 22 Ingenjörsskolan Electrum Forum Ingenjörsskolan Forum: Isafjordsgatan 39

5. Department of Microelectronics and Information Technology (IMIT) • The new department is organized in five labs, two sections, and two centers: • Laboratory of Materials and Semiconductor Physics • Laboratory of Solid State Devices • Laboratory of Optics, Photonics and Quantum Electronics • Laboratory of Electronics and Computer Systems • Laboratory of Communication Networks • Section for Telecommunication Systems • Section for Wireless Systems • KTH Online • Semiconductor Laboratory • The Department of Microelectronics and Information Technology was formed January 1st 2001 by merging the following departments and groups: • Department of Electronics (see this page for links to individual groups) • Department of Teleinformatics (see this page for links to individual groups) • Section of Materials Physics (Dept. of Physics) • Section of Condensed Matter Physics (Dept. of Physics) • Section of Optics (Dept. of Physics) • KTH Online • Semiconductor Laboratory

6. Laboratory of Electronics and Computer Systems (LECS) Research groups Prof. Hannu Tenhunen, Electronic Systems Design (ESD) Prof. Håkan Olsson, Radio and Analog Electronics (REL) Prof. Seif Haridi, Distributed Computer Systems (DCS) Prof. Mats Brorsson, Computer Theory and Engineering (CTE) Prof. Axel Jantsch, System Architecture and Methodology (SAM)

7. Education Research • >40 undergraduate courses • 7 professors • 16 teachers/scientists • ~200 HÅS (full year equivalent students) • ~50 PhD students • E-, D-, IT-, I MSc programs • SoC MSc program • Software systems • Performance evaluation • Theoretical aspects • Computer architecture • Electronic systems • Circuits and devices LECS LECS Activities Co-operation with industry

8. Hardware aspects LECS Research Parallel and Distributed Systems Software aspects Performance Evaluation of Computer Systems Distributed Computer Systems Computer Architecture System Architecture and Methods Electronic System Design Radio Electronics Circuits and Devices

9. Flip-chip bonder (~1um positioning accuracy) 8133A 33M-3GHz. 15ps TDR System (65GHz) (86100B + PSPL 15ps Pulse) Arbitrary Wave PCB Plotter (100um track) SoPC board Pattern Generator(2020A, 36Ch) Signal Sources (DC-3GHz) (30Hz-26.5GHz) E7405 EMC analyzer Package Test Fixtures, HF Probes, ISS, (DC- >40GHz) Logic Analyzers (TLA621, E9340A) System Simulation/Emulation and Prototyping

10. SoC Education Strategies:International Master Program on System-on-Chip Design

11. System-on-Chip int. M.Sc. Program: Socware Engineering www.ele.kth.se/SoC/ www.socware.com

12. IT-services and end-user behaviour Distributed and parallel processing Networking and protocols Digital communication and multimedia Software engineering Computer architectures adn compilers Embedded systems CASE/EDA/CAD VLSI systems and circuit design RF/analog/mixed signal IC desiign Semiconductor technology Electronic and system packaging New competence profiles needed Challenge: New breed of students than our generations

13. About the SoC Master Program • Globally the first master program on SoC, • start from 2000 • Students from worldwide • (Asia, Europe, African, S/N America) • Minim. Requirement • English (TOEFL 550/213, IELTS: 5.5, TWE 4.5) • Degree: BS/BE in EE, CS, CE (>120 CU) • Number of students • 2000: 23 [4 KTH (3 to Ph.D. study), 3 abroad, 15 industrial, 1 drop out] • 2001: 43 [15 KTH, ~15 industrial, ~12 abroad, 1 drop out] • 2002: 65 [start from Sept.2 2002] • 40 CU courses (24 oblig. +16 optional), 20 CU thesis • More information at: www.imit.kth.se/SOC

14. Course Name Credit  Units Quarter Embedded systems (A) Digital circuit design (B) Hardware modelling  (C) Digital hardware organization (A) Design of fault tolerant systems (A) SoC Architectures (A) Digital systems engineering (B) System modelling (C) Radio electronics (B) Anatomy of CAD tools for electronic design automation (C) Electronic system packaging/Mixed signal system design (B) Design documentation & IPR Issues (C) Low power analog & mixed signal IC's (B) System ASIC design (A) Special topics in SoC (A,B,C) Master's thesis (2nd year) (A-B-C) 5 5 4 4 4 4 5 5 5 5 5 4 5 5 4 20 1 1-2 1-2 2 2 3 3 3 3 3 4 4 4 4 4 1-2 Main Courses for SoC Master

15. Physical/Implementation view where the relevant features of technology are handled at different abstraction levels. Functional view where the proper abstract architectures and interfaces between different architectural elements are explored. Methodology view where the supporting design processes and organizational workflows, such as concurrent engineering, is covered for efficient and high quality execution of the design tasks. Different abstraction views in the curriculum

16. Researches inElectronic System Design Group Head: Prof. Hannu Tenhunen Faculty: Dr. Svante Signell (Ericsson Radio System) (Mixed signal SoC and DSP) Dr. Elena Dubrova (Logic synthesis, fault tolerance in SoC) Dr. Ana Rusu (ADC converter and mixed signal) Dr. Li-Rong Zheng (Interconnect centric SoC design and System-on-packaging)

17. On-Going Research Projects • Wideband Sigma-Delta A /D Conversion Techniques • COBRA- Data Converters for Broad Band Radio Systems • System-on-Chip for Mobile Internet • Wafer Level Packaging and Single Level Integrated Packaging Modules for High Frequency Wireless Communication Devices • Concurrent Packaging and VLSI Design for High-Frequency Circuits and Systems • Innovative RF/HF Blocks in System-on-Packaging Integration for Multi-band Multi-standard Radio Applications • Mixed Signal Design for System-on-Packaging Integration

18. On-Going Research Projects • Interconnect-Centric System-on-Chip Design for Network-on-Chip • Communication Platform Architectures for Gigascale Integration • Processor performance modeling • Low power DSP integration • Noise and interference analysis of mixers • Sampling architectures for software controlled receivers • Probabilistic Verification methodology for DSP ASICs • Level-Limited Optimization of Digital Logic Circuits • New Data Structure for Design Automation of Complex Systems • Fault Tolerance in System-on-a-Chip • NanoEDA: Architecture and design methodology for nano-scale electronic systems

19. Interconnect Strategies Global operation Low bandwidth High latency & High power The length increases 20 clocks Semi-global operation (between) 90,000 tracks Local, parallel operation high bandwidth Low latency & Low power The length scales down

20. Project Example: Interconnect Centric SoC Design 1 clock High Performance, small resource size

21. Physical Performance Estimation Wire Distribution Models: 1. Rent’s Rule 2. J. A. Davis, IEEE Trans. Electron Devices, vol.45, pp.580-589, 1998 3. J. P. Krusius, IEEE Trans. Adv. Packaging, vol.22, no.4, pp.642-648, 1999, NOCs alleviate the wring demand.

22. System level power delivery network High-Frequency on-chip global and semi-global lines Impedance (ohms) 0.025 0.020 0.015 0.010 0.005 0.000 High-Frequency Chip on SCM/MCM Mid-Frequency SCM/MCM on Board 1999 Target Impedance Low-Frequency Power Regulator 100 101 102 103 104 105 106 107 108 109 1010 Frequency (Hz) Research example: Power distribution for SoC

23. Example: Early Estimation of Physical Performance 0.18um CMOS with 6 metal layers M5 M6: Planned for power distribution Power Noise: < 10% Vdd (result: 25% of M5 and M6) Global signal & clock distribution (result: 75%) M3 M4: Semi-global wires M1 M2: Local wires Result of Crosstalk: < 20dB if f < 1GHz Result of Critical wire delay: result: 7.19 gate delay (M6) A priori power supply noise estimate. (169-pin C4-bonded multi-layer ceramic PGA package. 0.18mm CMOS, 6 Metal Layers).

24. Circuit switching, static routing, time division multiplexing, control is predetermined Packet switching, dynamic routing BPFT1 BPFR1 RF FDMA/CDMA Interconnects (wireless LAN type NOC/NOP) BPFT2 BPFR2 Optical Interconnects (SDH/SONET ATM type NOC/NOP Project Example: Interconnect Centric SoC for Network on Chip

25. DSP PCI Timer ROM RAM RISCMPU Ethernet Controller Memory Controller API SSP UART Watchdog bridge IP modules SSP SSP DSP RAM Loop filter VCO SSP API ROM Radio ASIC Balun Antenna Filter Switch Custom modules RF components RISCMPU Memory Controller Antenna Filter Ethernet Controller Switch System-on-package design example: co-simulation and system partitioning PCI VCO bridge Balun Radio ASIC Loop filter UART Timer Watchdog Project Example: Mixed Signal Implementation – SoC or SoP (1) Signal transmission and signal integrity; (2) System-timing and system performance; (3) Chip I/O design and power distribution; (4) Optimized system partitioning and system performance

26. Logic Memory Analog/RF Performance (function) Figure-of-Merit = Cost x Time-to-Market Everything is about Cost and Performance, and also Time-to-Market, then the implementation … SoC vs. SoP: • Definition of a system • Complete Functionality • Minimum I/Os • Hardware/Software • Mixed-signal (RF, analog, digital … MEMS, optical…) • Cost & Performance • System Performance • Cost for heterogeneous integration • Cost for mixed-signal isolation • Technology fusion • Intellectual property protection 1$ +1$ < 2$? 1$ +2$ > 3$? System-on-Chip system-on-package

27. For Further Information and Publications http://www.imit.kth.se/LECS Or e-mail to lrzheng@imit.kth.se