Fa Wang*, Wangyang Zhang*, Shupeng Sun*, Xin Li*, Chenjie Gu ┼

1. Bayesian Model Fusion: Large-Scale Performance Modeling of Analog and Mixed-Signal Circuits by Reusing Early-Stage Data Fa Wang*, Wangyang Zhang*, Shupeng Sun*, Xin Li*, Chenjie Gu┼ *ECE Dept. Carnegie Mellon University, Pittsburgh, PA 15213 ┼ Intel Corp. Hillsboro, OR 97124

2. Outline • Background • Bayesian Model Fusion • Experiment Results • Conclusion

3. Process Variations and Performance Modeling 65nm 45nm 32nm • Statistical performance modeling: approximate circuit performance as an analytical function of process variations • Performance model is a powerful tool for efficient circuit analysis: • Yield estimation • Corner extraction • Sensitivity analysis Small Size Large Variation f: circuit performance of interest (e.g. read delay of SRAM) ∆X: a vector of random variables to model process variations gi(∆X): basis functions (e.g., linear or quadratic polynomials) αi: model coefficients

4. Solving Performance Model: Least Squares Fitting (LSF) • Determine performance model Basis functions • LSF • A set of sampling points are collected • Model coefficients are solved from the following linear equation Model coefficients Total of M basis Total of K MC samples Basis M Basis 1 Basis 2 • The problem is required to be over-determined in order to be solvable (i.e. K > M)

5. Challenge: High Dimensionality • High dimensionality becomes a challenge in performance modeling • Large number of independent random variables must be used to describe variations in each transistor • Increased number of transistors in circuits • Example: a commercial 32nm CMOS process • ~40 random variables to model mismatches of a single transistor • Due to high dimensionality (i.e. large # of basis functions), it’s unrealistic to apply LSF (which requires # of MC samples> # of basis functions)

6. Sparsity • To handle the high dimensionality problem, sparsity feature of circuits has been explored[1] • Sparsity means that the circuit performance variability is only dominated by a few random variables • Example: In SRAM critical path, many Vth mismatches of transistors are not important • Performance model has a sparse profile: • Most of coefficients are zero or close to zero Model coefficients Performance Basis functions [1] X. Li, "Finding deterministic solution from underdetermined equation: large-scale performance modeling of analog/RF circuits," TCAD, vol. 29, no. 11, pp. 1661-1668, Nov. 2010

7. Sparse Regression • Sparse regression algorithm is an efficient performance modeling algorithm that utilizes the sparsity feature • Sparse regression is better than LSF because it requires less number of samples by using sparsity feature • Efficiency of performance modeling can be further improved, by considering additional information from design flow (will be discussed in detail later)

8. Outline • Background • Bayesian Model Fusion • Experiment Results • Conclusion

9. Bayesian Model Fusion (BMF): Overview • Key idea: BMF facilitates late stage performance modeling by reusing data collected in the early stage Late stage data Early stage data Traditional Performance modeling Performance modeling BMF Performance modeling Proposed

10. AMS Circuit Design Flow • Analog and mixed-signal (AMS) circuit design spans multiple stages Layout design stage Schematic design stage Designcycle for analog and mixed-signal circuits … Early stageLate stage Performance modeling … Performance modeling … Circuit modeling

11. Correlation in AMS Design Flow • One important fact in AMS design flow is that different stages share the same circuit topology and functionality Comparator: Layout stage Schematic stage • Leads to correlation among different stages

12. Correlation in Performance Models • Correlation: fE(∆X) and fL(∆X) are “likely” to be similar fE(∆X): early-stage performance model fL(∆X): late-stage performance model αEi,αLi : model coefficients gi(∆X): basis functions g1(∆X) g2(∆X) g3(∆X) g4(∆X) fE(∆X) fL(∆X)

13. The Proposed Algorithm Flow Early stage data Very few late stage data Prior Bayesian inference (Proposed) Early stage performance model Likelihood Late stage performance model Early stage Late stage

14. Prior • Prior is a distribution that describes the uncertainty of parameters based on early stage data, before late stage data is taken into account • In our work, information in early design stage is encoded in prior, which describes the uncertainty of late stage model coefficients pdf(αL,m) αL,m2 αL,m1 Lower Probability Higher Probability Prior distribution

15. Prior • Magnitude information of early-stage model coefficients is encoded in prior • Magnitude information here describes whether the absolute value of coefficient is relatively large or small • Small (or zero) coefficients information represents sparsity profile, which is essential for performance model[1] • Define prior distribution as a zero-mean Gaussian distribution • Key idea of encoding: the shape of prior is related to magnitude information Prior distribution [1] X. Li, "Finding deterministic solution from underdetermined equation: large-scale performance modeling of analog/RF circuits," TCAD, vol. 29, no. 11, pp. 1661-1668, Nov. 2010

16. Likelihood • Likelihood is a function of parameters, which evaluates how parameters fit with data • Late stage information is encoded in likelihood function • Specifically, late stage performance function information is encoded in likelihood function • In our work, likelihood function describes how well model coefficients fit with late stage data likelihood(αL,m) αL,m2 αL,m1 Likelihood Better fit Worse fit

17. Maximum-A-Posteriori Estimation • However, if we determine model coefficients solely based on likelihood, we may have over-fitting problem • In our case, # of samples in late stage is smaller than # of model coefficients in late stage • Bayesian’s theorem • Maximum-a-posteriori (MAP) estimation: pdf(αL) Posterior Likelihood Prior MAP estimation of αL likelihood(αL) Prior distribution Posterior Likelihood

18. Outline • Background • Bayesian Model Fusion • Experiment Results • Conclusion

19. SRAM Example • Example 1: CMOS SRAM • Designed in a commercial 32nm SOI • 61572 independent random process parameters are considered • Read delay is considered as performance • Linear performance model is fitted • Experiments run on a 2.5GHz Linux server with 16GB memory

20. Modeling Error • Two different methods are compared: • The proposed method (BMF) • Orthogonal Matching Pursuit (OMP) • Modeling error 4x

21. Modeling Time Speed-up • BMF requires 4x less samples to achieve similar accuracy as OMP in SRAM • 4x runtime speed-up to build performance model

22. RO Example • Example 2: CMOS ring oscillator • Designed in a commercial 32nm SOI • 7177 independent random process parameters are considered • Power, frequency and phase noise are considered as performance • Linear performance model is fitted • Experiments run on a 2.5GHz Linux server with 16GB memory

23. Modeling Error • Modeling error is measured for power, frequency and phase noise Power 9x Frequency Phase noise 9x 9x

24. Modeling Time Speed-up • BMF requires 9x less samples to achieve similar accuracy as OMP in RO • 9x runtime speed-up to build performance model

25. Conclusion • The proposed BMF method facilitates efficient high-dimensional performance modeling at late stage by reusing early stage data • BMF achieves more than 4x runtime speedup over traditional OMP method on SRAM and RO test cases • BMF can be used for commercial applications such as macro-modeling based verification