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选择的指令 ： Vadduhs Vsububs Vcmpgtsb Vandc vrlb

选择的指令 ： Vadduhs Vsububs Vcmpgtsb Vandc vrlb. Vadduhs ( Vector Add Unsigned Halfword Saturate). vadduhs d,a,b. For each vector element i from 0 to 7, do the following. Unsigned-integer halfword element i in a is added to unsigned-integer halfword element i in b

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选择的指令 ： Vadduhs Vsububs Vcmpgtsb Vandc vrlb

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  1. 选择的指令： Vadduhs Vsububs Vcmpgtsb Vandc vrlb

  2. Vadduhs(Vector Add Unsigned HalfwordSaturate) vadduhsd,a,b

  3. For each vector element ifrom 0 to 7, do the following. Unsigned-integer halfword element iin a is added to unsigned-integer halfword element iin b If the sum is greater than -1 the result saturates to -1. The low-order 16 bits of the result are placed into halfword element iof d.

  4. Vsububs(Vector Subtract Unsigned Byte Saturate) Vsububsd,a,b

  5. For each vector element ifrom 0 to 15, do the following. Unsigned-integer byte element iin b is subtracted from unsigned-integer byte element iin a. If the intermediate result is less than 0 the result saturates to 0. The low-order 8 bits of the result are placed into byte element iof d.

  6. Vcmpgtsb(Vector Compare Greater Than Signed Byte) vcmpgtsbd,b,a

  7. For each vector element ifrom 0 to 15, do the following. Signed-integer byte element iin VRA is compared to signed-integer byte element iin VRB. Byte element iin VRT is set to all 1s if signed-integer byte element iin VRA is greater than to signed-integer byte element iin VRB, and is set to all 0s otherwise

  8. Vandc(Vector Logical AND with Complement) vandc VRT,VRA,VRB

  9. VRT 􀁉 (VRA) & ¬(VRB) The contents of VRA are ANDed with the complementof the contents of VRB and the result is placed intoVRT.

  10. vrlb(Vector Rotate Left Byte) vrlb VRT,VRA,VRB

  11. For each vector element ifrom 0 to 15, do the following.Byteelement iin VRA is rotated left by the number of bits specified in the low-order 3 bits of the corresponding byte element iin VRB. The result is placed into byte element iin VRT.

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