Performed by: Yulia Turovski Lior Bar Lev Instructor: Mony Orbach

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Mid-Semester Presentation I Subject: High-Speed Communication Channel(s) Switch Performed by: Yulia Turovski Lior Bar Lev Instructor: Mony Orbach Winter semester 2010 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Outline • Reminder – Motivation and Goal • Switch structure • Switching algorithm (“Router”) • SerialLite II component • Packet size consideration • Implemented protocol • Validation method • Gantt diagram 2

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Motivation and Goal • Motivation: • High-speed communication between devices. • Utilizing high frequency achievable with new hardware. • Demand for reliable communication • Goal: • Design & implementation of high speed communication switch. • Use of advanced communication protocols. • Connect between as many devices as possible. • Best transmission rate possible. 2

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Priority vs. Data • SerialLite II can use two types of ports: • Priority ports • Sends packets with higher priority • Includes internal DLL functions (protocol described later) • Can stop data packet in middle of transmission • Will be routed by fullest queue first • Data ports • Sends “regular” packets • Example: video streaming • Doesn’t include internal DLL functions • We can implement one later • Will be routed by time priority using multiple-out queues Address 8bit Timestamp 16 bit Data 29Byte Data Priority Address 8bit Data 31Byte 2

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Priority Path Diagram config Routing Tables (RAM) Router out in out in out in in out FIFO FIFO FIFO FIFO SerialLite II SerialLite II SerialLite II SerialLite II 3

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Data Path Diagram config Routing Tables (RAM) Router out in out in out in in out Time priority queue Time priority queue Time priority queue Time priority queue SerialLite II SerialLite II SerialLite II SerialLite II 3

7. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Buffer Design • Entrance buffers offer 4 highest-priority packets each • Priority port presents oldest message available for each output port • Chosen for each port is the packet from the most occupied input queue • Data port presents the packet with earliest stamp for each output port • Chosen is the earliest-stamped packet for each output port • Each port can contribute 0-3 packets each cycle depending on availability and priority of packets. • Getting messages from inside the queue requires additional logic • Buffer-private stamping for fifo packets and priority logic 4

8. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Switching Algorithm • Translate addresses using translation tables • Hold start index • For each output port j • For each priority in port I (start index to N and then 1 to start-1) • Each buffer offers first message for each output port (4) • If size(i)>Max • Max=size(i), Pchoose(j)=i • Transfer Pchoose[j] • For each data in port I (start index to N and then 1 to start-1) • Each buffer offers oldest message for each output port (4) • If out(j).time<oldest(j) • Oldest(j)=i, Dchoose(j)= i • Transfer Dchoose[j] • Eventually we can implement each algorithm for any port 4

9. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות SerialLite II Megafunction • DLL and PHY • Multiple lanes • One lane per connection • Constant packet size • Small or large? • CRC checks included (16/32) • We use 16 • Physical layer enhancements • Buffers for quality of service • Holds up to 8 packets. • If full – no packets inserted • Optional use of flow control logic (costs space) 5

10. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות SerialLite II Limitations • Highest rate possible with stratix II GX – 6.75 Gbps • On other devices highest rate may be as low as 3.125 Gbps • Space resources for 4 SerialLite II ports with both priority and data packets (worst case scenario): • 1 Priority port: 1675 ALUTs + 1284 logic registers, 12 M512s and 22 M4K • 1 Data port: 1381 ALUTs + 1075 logic registers, 12 M512s and 12 M4K • Total, assuming ALUT=LREG=LE: 21660 LEs, 96 M512s and 136 M4Ks • Available: 90,960 LEs, 488 M512 and 408 M4Ks • Cores consume 24% of logic space and average of 25% of memory – reasonable for it’s advantages. 5

11. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Packet size consideration • Transfer rate – 6Gb/sec = 0.75GB/sec • Assuming clock frequency – 200 MHz • Transfer rate = clock frequency*packet size • Rate met for packets >= 3.75B • 16 byte packet allows blocking switching! 6

12. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Protocol • Priority packets • Every packet is a priority packet (no regulars) • Retry on error • Similar to selective repeat (NACK) • Characteristics of GBN (timeout, out of order) • Recovery. • Data packets have no built in DLL protocol 7

13. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Validation Method • Module with 4 SerialLite II instances • Random / Pre-prepared addressed packets (scenario) • Arranges two buffers for each port • After completion of transfer – comparing packets • Errors in switching • Errors in data • Order of reception vs. generation (stepper) • OFFLINE • In simulation – using test-bench • Possibility of adding test indicators (i.e. buffer full) • After synthesis – using another device 8

14. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Validation Method (2) Test device Switch Config Config out Port I Port I Port II gold gold gold gold res res res res Port II Port III Port III Port IV inX4 Port IV 2

15. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Project Schedule Minimum goal: showing each block and its simulation waves. Maximum goal: showing entire switch simulation with limited scenario test bench. 9